> Subject: RE: [PATCH v1 2/2] drm/i915/psr: clean register macro's name from > typo > > > Subject: [PATCH v1 2/2] drm/i915/psr: clean register macro's name from > > typo > > > > Apply s/_CONTINUOS_/_CONTINOUOS_/ for both > > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME and > > PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME. > > > > No functional change. > > > > Signed-off-by: Michał Grzelak <[email protected]> > > LGTM, > Reviewed-by: Suraj Kandpal <[email protected]> > > > --- > > drivers/gpu/drm/i915/display/intel_psr.c | 6 +++--- > > drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++-- > > 2 files changed, 5 insertions(+), 5 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > > b/drivers/gpu/drm/i915/display/intel_psr.c > > index 5bfac64284ef8..5e0cf34e1a819 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr.c > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > > @@ -1074,7 +1074,7 @@ static void dg2_activate_panel_replay(struct > > intel_dp > > *intel_dp) > > > > intel_de_rmw(display, > > PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), > > - 0, > > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); > > + 0, > > ADLP_PSR2_MAN_TRK_CTL_SF_CONTINOUOS_FULL_FRAME); > > > > intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), > > dp2_ctl_clear, dp2_ctl_set); } @@ -2618,8 +2618,8 @@ static u32 > > man_trk_ctl_partial_frame_bit_get(struct intel_display *display) > > static u32 man_trk_ctl_continuous_full_frame(struct intel_display *display) > > { > > return display->platform.alderlake_p || DISPLAY_VER(display) >= 14 ? > > - ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME : > > - PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME; > > + ADLP_PSR2_MAN_TRK_CTL_SF_CONTINOUOS_FULL_FRAME : > > + PSR2_MAN_TRK_CTL_SF_CONTINOUOS_FULL_FRAME; > > } > > > > static void intel_psr_force_update(struct intel_dp *intel_dp) diff > > --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > index a57bc111290d1..56df4d2f97286 100644 > > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h > > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h > > @@ -241,7 +241,7 @@ > > #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK > > REG_GENMASK(20, 11) > > #define PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) > > REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR_MASK > > , val) > > #define PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > > REG_BIT(3) > > -#define PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > > REG_BIT(2) > > +#define PSR2_MAN_TRK_CTL_SF_CONTINOUOS_FULL_FRAME > > REG_BIT(2) > > #define PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE > > REG_BIT(1) > > #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK > > REG_GENMASK(28, 16) > > #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) > > REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_START_ADD > > R_MASK, val) > > @@ -249,7 +249,7 @@ > > #define ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(val) > > REG_FIELD_PREP(ADLP_PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR > > _MASK, val) > > #define ADLP_PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE > > REG_BIT(31) > > #define ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME > > REG_BIT(14) > > -#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME > > REG_BIT(13) > > +#define ADLP_PSR2_MAN_TRK_CTL_SF_CONTINOUOS_FULL_FRAME > > REG_BIT(13)
*Continuous 😝 With that fixed LGTM Reviewed-by: Suraj Kandpal <[email protected]> > > > > #define _LNL_SFF_CTL_A 0x60918 > > #define _LNL_SFF_CTL_B 0x61918 > > -- > > 2.45.2
