On Mon, Mar 24, 2014 at 11:00:07PM +0530, [email protected] wrote:
> From: Akash Goel <[email protected]>
>
> For disabling L3 clock gating we need to set bit 25 of MMIO
> register 940c. Earlier this was being done by just writing 1
> into bit 25 and resetting all other bits.
> This patch modifies the routine to read-modify-write of the
> register, so that the values of other bits are not destroyed.
>
> v2: Modifying the comments and the patch commit message (Chris)
>
> Signed-off-by: Akash Goel <[email protected]>
> Signed-off-by: Sourab Gupta <[email protected]>
Apart from the multiline comment format and the second line not aligned
with the '(' as we usually do:
Reviewed-by: Damien Lespiau <[email protected]>
--
Damien
> ---
> drivers/gpu/drm/i915/intel_pm.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c3a8554..af4bb8e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5093,8 +5093,11 @@ static void valleyview_init_clock_gating(struct
> drm_device *dev)
> I915_WRITE(GEN6_UCGCTL2,
> GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
>
> - /* WaDisableL3Bank2xClockGate:vlv */
> - I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
> + /* WaDisableL3Bank2xClockGate:vlv
> + * Disabling L3 clock gating- MMIO 940c[25] = 1
> + * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
> + I915_WRITE(GEN7_UCGCTL4,
> + I915_READ(GEN7_UCGCTL4) |
> GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
>
> I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
>
> --
> 1.8.5.1
>
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