On Tue, May 27, 2014 at 03:27:23PM +0100, Damien Lespiau wrote: > On Mon, Mar 24, 2014 at 11:00:07PM +0530, [email protected] wrote: > > From: Akash Goel <[email protected]> > > > > For disabling L3 clock gating we need to set bit 25 of MMIO > > register 940c. Earlier this was being done by just writing 1 > > into bit 25 and resetting all other bits. > > This patch modifies the routine to read-modify-write of the > > register, so that the values of other bits are not destroyed. > > > > v2: Modifying the comments and the patch commit message (Chris) > > > > Signed-off-by: Akash Goel <[email protected]> > > Signed-off-by: Sourab Gupta <[email protected]> > > Apart from the multiline comment format and the second line not aligned > with the '(' as we usually do:
Fixed. > Reviewed-by: Damien Lespiau <[email protected]> Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
