On Mon, Jul 28, 2014 at 07:56:27PM +0100, [email protected] wrote: > From: Rafael Barbalho <[email protected]> > > According to the specifications bit 6 is actually valid in the stride > register. > > Cc: Jesse Barnes <[email protected]> > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Rafael Barbalho <[email protected]>
Indeed, min stride alignment is 64 bytes so we want bit 6 as well. Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 99eb7ca..52dab31 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6221,7 +6221,7 @@ static void i9xx_get_plane_config(struct intel_crtc > *crtc, > crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; > > val = I915_READ(DSPSTRIDE(pipe)); > - crtc->base.primary->fb->pitches[0] = val & 0xffffff80; > + crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; > > aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, > plane_config->tiled); > @@ -7241,7 +7241,7 @@ static void ironlake_get_plane_config(struct intel_crtc > *crtc, > crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; > > val = I915_READ(DSPSTRIDE(pipe)); > - crtc->base.primary->fb->pitches[0] = val & 0xffffff80; > + crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; > > aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, > plane_config->tiled); > -- > 2.0.3 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
