On Tue, Jul 29, 2014 at 08:04:59PM +0200, Daniel Vetter wrote:
> On Tue, Jul 29, 2014 at 10:01:57AM -0700, Jesse Barnes wrote:
> > On Sat, 28 Jun 2014 02:04:25 +0300
> > ville.syrj...@linux.intel.com wrote:
> >
> > > From: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > >
> > > CHV supports DP training pattern 3. Add the required stuff.
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_reg.h | 2 ++
> > > drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++----
> > > 2 files changed, 16 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > b/drivers/gpu/drm/i915/i915_reg.h
> > > index 85b59c4..8debe61 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3515,6 +3515,8 @@ enum punit_power_well {
> > > #define DP_LINK_TRAIN_OFF (3 << 28)
> > > #define DP_LINK_TRAIN_MASK (3 << 28)
> > > #define DP_LINK_TRAIN_SHIFT 28
> > > +#define DP_LINK_TRAIN_PAT_3_CHV (1 << 14)
> > > +#define DP_LINK_TRAIN_MASK_CHV ((3 << 28)|(1<<14))
> > >
> > > /* CPT Link training mode */
> > > #define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index 739dc43..a825ff1 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -2900,7 +2900,10 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > > }
> > >
> > > } else {
> > > - *DP &= ~DP_LINK_TRAIN_MASK;
> > > + if (IS_CHERRYVIEW(dev))
> > > + *DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > + else
> > > + *DP &= ~DP_LINK_TRAIN_MASK;
> > >
> > > switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> > > case DP_TRAINING_PATTERN_DISABLE:
> > > @@ -2913,8 +2916,12 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> > > *DP |= DP_LINK_TRAIN_PAT_2;
> > > break;
> > > case DP_TRAINING_PATTERN_3:
> > > - DRM_ERROR("DP training pattern 3 not supported\n");
> > > - *DP |= DP_LINK_TRAIN_PAT_2;
> > > + if (IS_CHERRYVIEW(dev)) {
> > > + *DP |= DP_LINK_TRAIN_PAT_3_CHV;
> > > + } else {
> > > + DRM_ERROR("DP training pattern 3 not
> > > supported\n");
> > > + *DP |= DP_LINK_TRAIN_PAT_2;
> > > + }
> > > break;
> > > }
> > > }
> > > @@ -3201,7 +3208,10 @@ intel_dp_link_down(struct intel_dp *intel_dp)
> > > DP &= ~DP_LINK_TRAIN_MASK_CPT;
> > > I915_WRITE(intel_dp->output_reg, DP |
> > > DP_LINK_TRAIN_PAT_IDLE_CPT);
> > > } else {
> > > - DP &= ~DP_LINK_TRAIN_MASK;
> > > + if (IS_CHERRYVIEW(dev))
> > > + DP &= ~DP_LINK_TRAIN_MASK_CHV;
> > > + else
> > > + DP &= ~DP_LINK_TRAIN_MASK;
> > > I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
> > > }
> > > POSTING_READ(intel_dp->output_reg);
> >
> > I guess we could have a whole IS_CHV block, but that would probably add
> > more code than it saved...
> >
> > Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
>
> This won't do a hole lot without adding HBR2 support ... Queued for
> -next anyway, thanks for the patch.
What else is missing for HBR2?
--
Ville Syrjälä
Intel OTC
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