On Mon, Feb 16, 2015 at 03:08:01PM +0530, Vijay Purushothaman wrote: > Initialize lock detect threshold and select coarse threshold if M2 is > zero
"if M2 fractional part is zero"? > > Signed-off-by: Vijay Purushothaman <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 87d1721..ae2a77f 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6085,11 +6085,22 @@ static void chv_prepare_pll(struct intel_crtc *crtc, > dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); > vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); > > + /* Program digital lock detect threshold */ > + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); > + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); Again need to clear out the old bits first. > + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); > + > } else { > /* M2 fraction division disable */ > dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); > dpio_val &= ~(DPIO_CHV_FRAC_DIV_EN); > vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); > + > + /* Program digital lock detect threshold */ > + dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); > + dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); Ditto. > + dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; > + vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); > } > > /* Loop filter */ > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
