On Fri, May 22, 2015 at 11:22:39AM +0300, Mika Kahola wrote: > From: Ville Syrjälä <[email protected]> > > Bspec says we shouldn't enable IPS on BDW when the pipe pixel rate > exceeds 95% of the core display clock. Apparently this can cause > underruns. > > There's no similar restriction listed for HSW, so leave that one alone > for now. > > v2: Add pipe_config_supports_ips() (Chris) > v3: Compare against the max cdclk insted of the current cdclk > > Tested-by: Timo Aaltonen <[email protected]> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=83497 > Signed-off-by: Ville Syrjälä <[email protected]> > > v4: Rebased to the latest > v5: Rebased to the latest > > Reviewed-by: Mika Kahola <[email protected]> > > Author: Ville Syrjälä <[email protected]> > ---
Reviewed-by: Damien Lespiau <[email protected]> -- Damien > drivers/gpu/drm/i915/intel_display.c | 30 ++++++++++++++++++++++++++++-- > drivers/gpu/drm/i915/intel_drv.h | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 17 ++++++++--------- > 3 files changed, 37 insertions(+), 12 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 7db1eee..febf993 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -6406,12 +6406,38 @@ retry: > return ret; > } > > +static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, > + struct intel_crtc_state *pipe_config) > +{ > + if (pipe_config->pipe_bpp > 24) > + return false; > + > + /* HSW can handle pixel rate up to cdclk? */ > + if (IS_HASWELL(dev_priv->dev)) > + return true; > + > + /* > + * FIXME if we compare against max we should then > + * increase the cdclk frequency when the current > + * value is too low. The other option is to compare > + * against the cdclk frequency we're going have post > + * modeset (ie. one we computed using other constraints). > + * Need to measure whether using a lower cdclk w/o IPS > + * is better or worse than a higher cdclk w/ IPS. > + */ > + return ilk_pipe_pixel_rate(pipe_config) <= > + dev_priv->max_cdclk_freq * 95 / 100; > +} > + > static void hsw_compute_ips_config(struct intel_crtc *crtc, > struct intel_crtc_state *pipe_config) > { > + struct drm_device *dev = crtc->base.dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + > pipe_config->ips_enabled = i915.enable_ips && > - hsw_crtc_supports_ips(crtc) && > - pipe_config->pipe_bpp <= 24; > + hsw_crtc_supports_ips(crtc) && > + pipe_config_supports_ips(dev_priv, pipe_config); > } > > static int intel_crtc_compute_config(struct intel_crtc *crtc, > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index 47bc729..09df4b5 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1371,7 +1371,7 @@ void ilk_wm_get_hw_state(struct drm_device *dev); > void skl_wm_get_hw_state(struct drm_device *dev); > void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, > struct skl_ddb_allocation *ddb /* out */); > - > +uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config); > > /* intel_sdvo.c */ > bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool > is_sdvob); > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 0046cb4..282ad59 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1434,23 +1434,22 @@ static void i845_update_wm(struct drm_crtc > *unused_crtc) > I915_WRITE(FW_BLC, fwater_lo); > } > > -static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, > - struct drm_crtc *crtc) > +uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) > { > - struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > uint32_t pixel_rate; > > - pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; > + pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; > > /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to > * adjust the pixel_rate here. */ > > - if (intel_crtc->config->pch_pfit.enabled) { > + if (pipe_config->pch_pfit.enabled) { > uint64_t pipe_w, pipe_h, pfit_w, pfit_h; > - uint32_t pfit_size = intel_crtc->config->pch_pfit.size; > + uint32_t pfit_size = pipe_config->pch_pfit.size; > + > + pipe_w = pipe_config->pipe_src_w; > + pipe_h = pipe_config->pipe_src_h; > > - pipe_w = intel_crtc->config->pipe_src_w; > - pipe_h = intel_crtc->config->pipe_src_h; > pfit_w = (pfit_size >> 16) & 0xFFFF; > pfit_h = pfit_size & 0xFFFF; > if (pipe_w < pfit_w) > @@ -2066,7 +2065,7 @@ static void ilk_compute_wm_parameters(struct drm_crtc > *crtc, > > p->active = true; > p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; > - p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); > + p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config); > > if (crtc->primary->state->fb) > p->pri.bytes_per_pixel = > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
