From: Ville Syrjälä <[email protected]> Since intel_gen4_compute_page_offset() can now handle tiling formats all the way down to gen2, rename it to intel_compute_page_offset(). Not that we actually use it on gen2/3 since there's no DSPSURF etc. registers which would take a page aligned address.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/intel_display.c | 24 +++++++++++------------- drivers/gpu/drm/i915/intel_drv.h | 10 +++++----- drivers/gpu/drm/i915/intel_sprite.c | 22 +++++++++------------- 3 files changed, 25 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 509fcac..75be66b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2453,11 +2453,11 @@ static void intel_unpin_fb_obj(struct drm_framebuffer *fb, /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel * is assumed to be a power-of-two. */ -unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, - int *x, int *y, - uint64_t fb_modifier, - unsigned int cpp, - unsigned int pitch) +unsigned long intel_compute_page_offset(struct drm_i915_private *dev_priv, + int *x, int *y, + uint64_t fb_modifier, + unsigned int cpp, + unsigned int pitch) { if (fb_modifier != DRM_FORMAT_MOD_NONE) { unsigned int tile_size, tile_width, tile_height; @@ -2766,10 +2766,9 @@ static void i9xx_update_primary_plane(struct drm_crtc *crtc, if (INTEL_INFO(dev)->gen >= 4) { intel_crtc->dspaddr_offset = - intel_gen4_compute_page_offset(dev_priv, - &x, &y, fb->modifier[0], - pixel_size, - fb->pitches[0]); + intel_compute_page_offset(dev_priv, &x, &y, + fb->modifier[0], pixel_size, + fb->pitches[0]); linear_offset -= intel_crtc->dspaddr_offset; } else { intel_crtc->dspaddr_offset = linear_offset; @@ -2871,10 +2870,9 @@ static void ironlake_update_primary_plane(struct drm_crtc *crtc, linear_offset = y * fb->pitches[0] + x * pixel_size; intel_crtc->dspaddr_offset = - intel_gen4_compute_page_offset(dev_priv, - &x, &y, fb->modifier[0], - pixel_size, - fb->pitches[0]); + intel_compute_page_offset(dev_priv, &x, &y, + fb->modifier[0], pixel_size, + fb->pitches[0]); linear_offset -= intel_crtc->dspaddr_offset; if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { dspcntr |= DISPPLANE_ROTATE_180; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 429f744..a12ac95 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1135,11 +1135,11 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state); #define assert_pipe_enabled(d, p) assert_pipe(d, p, true) #define assert_pipe_disabled(d, p) assert_pipe(d, p, false) -unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, - int *x, int *y, - uint64_t fb_modifier, - unsigned int cpp, - unsigned int pitch); +unsigned long intel_compute_page_offset(struct drm_i915_private *dev_priv, + int *x, int *y, + uint64_t fb_modifier, + unsigned int cpp, + unsigned int pitch); void intel_prepare_reset(struct drm_device *dev); void intel_finish_reset(struct drm_device *dev); void hsw_enable_pc8(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 4a1a5f4..6614adb 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -420,11 +420,9 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc, crtc_h--; linear_offset = y * fb->pitches[0] + x * pixel_size; - sprsurf_offset = intel_gen4_compute_page_offset(dev_priv, - &x, &y, - fb->modifier[0], - pixel_size, - fb->pitches[0]); + sprsurf_offset = intel_compute_page_offset(dev_priv, &x, &y, + fb->modifier[0], pixel_size, + fb->pitches[0]); linear_offset -= sprsurf_offset; if (dplane->state->rotation == BIT(DRM_ROTATE_180)) { @@ -554,10 +552,9 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h; linear_offset = y * fb->pitches[0] + x * pixel_size; - sprsurf_offset = - intel_gen4_compute_page_offset(dev_priv, - &x, &y, fb->modifier[0], - pixel_size, fb->pitches[0]); + sprsurf_offset = intel_compute_page_offset(dev_priv, &x, &y, + fb->modifier[0], pixel_size, + fb->pitches[0]); linear_offset -= sprsurf_offset; if (plane->state->rotation == BIT(DRM_ROTATE_180)) { @@ -692,10 +689,9 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h; linear_offset = y * fb->pitches[0] + x * pixel_size; - dvssurf_offset = - intel_gen4_compute_page_offset(dev_priv, - &x, &y, fb->modifier[0], - pixel_size, fb->pitches[0]); + dvssurf_offset = intel_compute_page_offset(dev_priv, &x, &y, + fb->modifier[0], pixel_size, + fb->pitches[0]); linear_offset -= dvssurf_offset; if (plane->state->rotation == BIT(DRM_ROTATE_180)) { -- 2.4.9 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
