On Wed, Nov 04, 2015 at 07:24:18PM +0200, Imre Deak wrote: > Suppressing LCPLL disabling was added to avoid interfering with the DMC > firmware. It is not needed any more since we uninit CDCLK now with the > DMC deactivated (DC states disabled). We also must disable it during system > suspend as part of the Bspec "Display uninit sequence". > > Signed-off-by: Imre Deak <[email protected]>
Reviewed-by: Patrik Jakobsson <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 14 ++++---------- > 1 file changed, 4 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index d9ed128..d0fec07 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5691,16 +5691,10 @@ void skl_uninit_cdclk(struct drm_i915_private > *dev_priv) > if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) > DRM_ERROR("DBuf power disable timeout\n"); > > - /* > - * DMC assumes ownership of LCPLL and will get confused if we touch it. > - */ > - if (dev_priv->csr.dmc_payload) { > - /* disable DPLL0 */ > - I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & > - ~LCPLL_PLL_ENABLE); > - if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) > - DRM_ERROR("Couldn't disable DPLL0\n"); > - } > + /* disable DPLL0 */ > + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); > + if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) > + DRM_ERROR("Couldn't disable DPLL0\n"); > } > > void skl_init_cdclk(struct drm_i915_private *dev_priv) > -- > 2.1.4 > _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
