On Wed, Nov 25, 2015 at 05:11:23PM +0200, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > LPT/WPT only have transcoder A, so we shouldn't look at FIFO underruns > for transocoder B/C. And more importnatnly we should not consider > the state of underrun reporting for transcoders B/C when checking > whether we can enable the south error interrupt. > > The whole thing is a bit of mess since we store the underrun reporting > state for transcoder A under intel_crtc for pipe A, irrespective of > which pipe may actually be driving the transcoder. But I figured trying > to change that would result in more churn. > > Caveat: totally untested due to lack of hw, but might explain some of > the HSW/BDW BAT fails...
Hmm. Actually it can't since we don't use the CRCs that get signalled via the south error interrupt. Back to the drawing board... > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_fifo_underrun.c | 24 ++++++++++++++++++++---- > 1 file changed, 20 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c > b/drivers/gpu/drm/i915/intel_fifo_underrun.c > index bda526660e20..04bf625a1b6c 100644 > --- a/drivers/gpu/drm/i915/intel_fifo_underrun.c > +++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c > @@ -48,6 +48,13 @@ > * The code also supports underrun detection on the PCH transcoder. > */ > > +static bool cpt_transcoder_exists(struct drm_i915_private *dev_priv, > + enum transcoder pch_transcoder) > +{ > + /* HSW/BDW have only transcoder A */ > + return !HAS_DDI(dev_priv) || pch_transcoder == TRANSCODER_A; > +} > + > static bool ivb_can_enable_err_int(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -69,13 +76,16 @@ static bool ivb_can_enable_err_int(struct drm_device *dev) > static bool cpt_can_enable_serr_int(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > - enum pipe pipe; > - struct intel_crtc *crtc; > + enum transcoder pch_transcoder; > > assert_spin_locked(&dev_priv->irq_lock); > > - for_each_pipe(dev_priv, pipe) { > - crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); > + for_each_pipe(dev_priv, pch_transcoder) { > + struct intel_crtc *crtc = > + > to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pch_transcoder]); > + > + if (!cpt_transcoder_exists(dev_priv, pch_transcoder)) > + continue; > > if (crtc->pch_fifo_underrun_disabled) > return false; > @@ -206,6 +216,9 @@ static void cpt_check_pch_fifo_underruns(struct > intel_crtc *crtc) > > assert_spin_locked(&dev_priv->irq_lock); > > + if (!cpt_transcoder_exists(dev_priv, pch_transcoder)) > + return; > + > if ((serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)) == 0) > return; > > @@ -222,6 +235,9 @@ static void cpt_set_fifo_underrun_reporting(struct > drm_device *dev, > { > struct drm_i915_private *dev_priv = dev->dev_private; > > + if (!cpt_transcoder_exists(dev_priv, pch_transcoder)) > + return; > + > if (enable) { > I915_WRITE(SERR_INT, > SERR_INT_TRANS_FIFO_UNDERRUN(pch_transcoder)); > -- > 2.4.10 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
