On Thu, 18 Feb 2016, Jani Nikula <[email protected]> wrote:
> From: Uma Shankar <[email protected]>
>
> DSP CLK_GATE registers are specific to BYT and CHT.
> Avoid programming the same for BXT platform.
>
> v2: Rebased on latest drm nightly branch.
>
> v3: Fixed Jani's review comments
>
> Signed-off-by: Uma Shankar <[email protected]>
> Signed-off-by: Jani Nikula <[email protected]>
I gave up hoping to get CI results for this one, after two attempts. We
have no coverage for this function anyway, and I've tested this before
to not break BYT. Thus pushed to drm-intel-next-queued.
BR,
Jani.
> ---
> drivers/gpu/drm/i915/intel_dsi.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> b/drivers/gpu/drm/i915/intel_dsi.c
> index fcd746c55abd..b928c503df24 100644
> --- a/drivers/gpu/drm/i915/intel_dsi.c
> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> @@ -634,7 +634,6 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder)
> {
> struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> - u32 val;
>
> DRM_DEBUG_KMS("\n");
>
> @@ -642,9 +641,13 @@ static void intel_dsi_post_disable(struct intel_encoder
> *encoder)
>
> intel_dsi_clear_device_ready(encoder);
>
> - val = I915_READ(DSPCLK_GATE_D);
> - val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> - I915_WRITE(DSPCLK_GATE_D, val);
> + if (!IS_BROXTON(dev_priv)) {
> + u32 val;
> +
> + val = I915_READ(DSPCLK_GATE_D);
> + val &= ~DPOUNIT_CLOCK_GATE_DISABLE;
> + I915_WRITE(DSPCLK_GATE_D, val);
> + }
>
> drm_panel_unprepare(intel_dsi->panel);
--
Jani Nikula, Intel Open Source Technology Center
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