On Thu, Apr 14, 2016 at 10:36:00AM +0100, Chris Wilson wrote: > On Wed, Apr 13, 2016 at 09:19:51PM +0300, [email protected] wrote: > > From: Ville Syrjälä <[email protected]> > > > > On VLV/CHV the master interrupt enable bit only affects GT/PM > > interrupts. Display interrupts are not affected by the master > > irq control. > > > > Also it seems that the CPU interrupt will only be generated when > > the combined result of all GT/PM/display interrupts has a 0->1 > > edge. We already use the master interrupt enable bit to make sure > > GT/PM interrupt can generate such an edge if we don't end up clearing > > all IIR bits. We must do the same for display interrupts, and for > > that we can simply clear out VLV_IER, and restore after we've acked > > all the interrupts we are about to process. > > > > So with both master interrupt enable and VLV_IER cleared out, we will > > guarantee that there will be a 0->1 edge if any IIR bits are still set > > at the end, and thus another CPU interrupt will be generated. > > > > Cc: Chris Wilson <[email protected]> > > Cc: Tvrtko Ursulin <[email protected]> > > Fixes: 579de73b048a ("drm/i915: Exit cherryview_irq_handler() after one > > pass") > > Signed-off-by: Ville Syrjälä <[email protected]> > > Ville is very persuasive, > Reviewed-by: Chris Wilson <[email protected]> > > Other than wishing the extra POSTING_READ and reading known registers > away, the rest of the series is also > Reviewed-by: Chris Wilson <[email protected]>
Entire series pushed to dinq. Thanks for the review. Let's keep our fingers crossed that this cures all the current chv ailments. -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
