On ma, 2016-04-25 at 13:30 +0100, Chris Wilson wrote:
> On Mon, Apr 25, 2016 at 03:23:20PM +0300, Imre Deak wrote:
> > Use named struct initializers for clarity. Also fix the target cache
> > definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0
> > meant ELLC but on GEN9+ it means the TC and LRU controls are taken from
> > the PTE.
> >
> > No functional change.
> >
> > Signed-off-by: Imre Deak <imre.d...@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_mocs.c | 79
> > ++++++++++++++++++++++++++-------------
> > 1 file changed, 52 insertions(+), 27 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_mocs.c
> > b/drivers/gpu/drm/i915/intel_mocs.c
> > index 23b8545..5006a92 100644
> > --- a/drivers/gpu/drm/i915/intel_mocs.c
> > +++ b/drivers/gpu/drm/i915/intel_mocs.c
> > @@ -66,9 +66,10 @@ struct drm_i915_mocs_table {
> > #define L3_WB 3
> >
> > /* Target cache */
> > -#define ELLC 0
> > -#define LLC 1
> > -#define LLC_ELLC 2
> > +#define LE_TC_PAGETABLE 0
> > +#define LE_TC_LLC 1
> > +#define LE_TC_LLC_ELLC 2
> > +#define LE_TC_LLC_ELLC_ALT 3
> >
> > /*
> > * MOCS tables
> > @@ -96,34 +97,58 @@ struct drm_i915_mocs_table {
> > * end.
> > */
> > static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
> > - /* { 0x00000009, 0x0010 } */
>
> Hmm, we lose this convenience. Since we have the same table in userspace
> to check the ABI is maintained, it would be nice to keep around.
Ok, I can add them back.
> Also mention that you ran igt/gem_mocs_settings to confirm no changes.
Ok, didn't know about this patch. After patch 2/2 there is a change in
the 3rd entry but that's expected based on the explanation of the
commit message there. So I can fix the test case accordingly.
--Imre
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