On Mon, Apr 25, 2016 at 03:23:20PM +0300, Imre Deak wrote: > Use named struct initializers for clarity. Also fix the target cache > definition to reflect its role in GEN9 onwards. On GEN8 a TC value of 0 > meant ELLC but on GEN9+ it means the TC and LRU controls are taken from > the PTE. > > No functional change. > > Signed-off-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/intel_mocs.c | 79 > ++++++++++++++++++++++++++------------- > 1 file changed, 52 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_mocs.c > b/drivers/gpu/drm/i915/intel_mocs.c > index 23b8545..5006a92 100644 > --- a/drivers/gpu/drm/i915/intel_mocs.c > +++ b/drivers/gpu/drm/i915/intel_mocs.c > @@ -66,9 +66,10 @@ struct drm_i915_mocs_table { > #define L3_WB 3 > > /* Target cache */ > -#define ELLC 0 > -#define LLC 1 > -#define LLC_ELLC 2 > +#define LE_TC_PAGETABLE 0 > +#define LE_TC_LLC 1 > +#define LE_TC_LLC_ELLC 2 > +#define LE_TC_LLC_ELLC_ALT 3 > > /* > * MOCS tables > @@ -96,34 +97,58 @@ struct drm_i915_mocs_table { > * end. > */ > static const struct drm_i915_mocs_entry skylake_mocs_table[] = { > - /* { 0x00000009, 0x0010 } */
Hmm, we lose this convenience. Since we have the same table in userspace to check the ABI is maintained, it would be nice to keep around. Also mention that you ran igt/gem_mocs_settings to confirm no changes. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
