On Wed, 11 May 2016, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > Make thins a bit easier to read by extracting the SKL DPLL0 > disable into separate functions. We already have the enable > counterpart. Down the line this will also help make the cdclk > programming on SKL, BXT, and following platforms look rather > consistent. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 57ff51172065..0186f775f353 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5610,6 +5610,14 @@ skl_dpll0_enable(struct drm_i915_private *dev_priv, > unsigned int required_vco) > DRM_ERROR("DPLL0 not locked\n"); > } > > +static void > +skl_dpll0_disable(struct drm_i915_private *dev_priv) > +{ > + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); > + if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) > + DRM_ERROR("Couldn't disable DPLL0\n"); > +} > + > static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) > { > int ret; > @@ -5695,10 +5703,7 @@ void skl_uninit_cdclk(struct drm_i915_private > *dev_priv) > if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) > DRM_ERROR("DBuf power disable timeout\n"); > > - /* disable DPLL0 */ > - I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); > - if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) > - DRM_ERROR("Couldn't disable DPLL0\n"); > + skl_dpll0_disable(dev_priv); > } > > void skl_init_cdclk(struct drm_i915_private *dev_priv) -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
