[Intel-gfx] [PATCH 4/6] drm/i915: Move VLV divider readout to intel_dpio_phy.c

[Ander Conselvan de Oliveira]

Reading the dividers depends on sideband messaging, so it fits well if
the other functions in intel_dpio_phy.c. The new function will also be
used in a future patch.

Signed-off-by: Ander Conselvan de Oliveira 
<ander.conselvan.de.olive...@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h       |  2 ++
 drivers/gpu/drm/i915/intel_display.c  | 11 +----------
 drivers/gpu/drm/i915/intel_dpio_phy.c | 16 ++++++++++++++++
 3 files changed, 19 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 99dfacd..7dfa555 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3640,6 +3640,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder);
 void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 bestn,
                         u32 bestm1, u32 bestm2, u32 bestp1, u32 bestp2,
                         int port_clock, bool dp);
+void vlv_phy_read_dividers(struct drm_i915_private *dev_priv,
+                          enum pipe pipe, struct intel_dpll *clock);
 
 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 3e494ec..8d61263 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7806,22 +7806,13 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe = pipe_config->cpu_transcoder;
        struct intel_dpll clock;
-       u32 mdiv;
        int refclk = 100000;
 
        /* In case of DSI, DPLL will not be used */
        if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
                return;
 
-       mutex_lock(&dev_priv->sb_lock);
-       mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
-       mutex_unlock(&dev_priv->sb_lock);
-
-       clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
-       clock.m2 = mdiv & DPIO_M2DIV_MASK;
-       clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
-       clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
-       clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+       vlv_phy_read_dividers(dev_priv, pipe, &clock);
 
        pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
 }
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c 
b/drivers/gpu/drm/i915/intel_dpio_phy.c
index fcadc92..d28ef9f 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -670,3 +670,19 @@ void vlv_phy_prepare_pll(struct intel_crtc *crtc, u32 
bestn,
        vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
        mutex_unlock(&dev_priv->sb_lock);
 }
+
+void vlv_phy_read_dividers(struct drm_i915_private *dev_priv,
+                          enum pipe pipe, struct intel_dpll *clock)
+{
+       u32 mdiv;
+
+       mutex_lock(&dev_priv->sb_lock);
+       mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
+       mutex_unlock(&dev_priv->sb_lock);
+
+       clock->m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
+       clock->m2 = mdiv & DPIO_M2DIV_MASK;
+       clock->n = (mdiv >> DPIO_N_SHIFT) & 0xf;
+       clock->p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
+       clock->p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
+}
-- 
2.5.5

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