With the bulk of the dpio code moved out of the vlv/chv prepare pll
functions into intel_dpio_phy.c, those functions became simple enough
that they can be merged with the pll enabling function, that always
succeeds the prepare call.
Signed-off-by: Ander Conselvan de Oliveira
<ander.conselvan.de.olive...@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 82 ++++++++++++------------------------
1 file changed, 26 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 06d9b96..3e494ec 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -104,10 +104,6 @@ static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc,
static void ironlake_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipeconf(struct drm_crtc *crtc);
static void haswell_set_pipemisc(struct drm_crtc *crtc);
-static void vlv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config);
-static void chv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config);
static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state
*);
static void skl_init_scalers(struct drm_device *dev, struct intel_crtc
*intel_crtc,
@@ -1547,6 +1543,19 @@ static void vlv_enable_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
+ /* Enable Refclk */
+ I915_WRITE(DPLL(pipe),
+ pipe_config->dpll_hw_state.dpll &
+ ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
+
+ /* No need to actually set up the DPLL with DSI */
+ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0)
+ vlv_phy_prepare_pll(crtc, pipe_config->dpll.n,
+ pipe_config->dpll.m1, pipe_config->dpll.m2,
+ pipe_config->dpll.p1, pipe_config->dpll.p2,
+ pipe_config->port_clock,
+ pipe_config->has_dp_encoder);
+
assert_pipe_disabled(dev_priv, pipe);
/* PLL is protected by panel, make sure we can write it */
@@ -1596,6 +1605,17 @@ static void chv_enable_pll(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
+ /* Enable Refclk and SSC */
+ I915_WRITE(DPLL(pipe),
+ pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
+
+ /* No need to actually set up the DPLL with DSI */
+ if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) != 0)
+ chv_phy_prepare_pll(crtc, pipe_config->dpll.n,
+ pipe_config->dpll.m1, pipe_config->dpll.m2,
+ pipe_config->dpll.p1, pipe_config->dpll.p2,
+ pipe_config->dpll.vco);
+
assert_pipe_disabled(dev_priv, pipe);
/* PLL is protected by panel, make sure we can write it */
@@ -6086,13 +6106,10 @@ static void valleyview_crtc_enable(struct drm_crtc
*crtc)
if (encoder->pre_pll_enable)
encoder->pre_pll_enable(encoder);
- if (IS_CHERRYVIEW(dev)) {
- chv_prepare_pll(intel_crtc, intel_crtc->config);
+ if (IS_CHERRYVIEW(dev))
chv_enable_pll(intel_crtc, intel_crtc->config);
- } else {
- vlv_prepare_pll(intel_crtc, intel_crtc->config);
+ else
vlv_enable_pll(intel_crtc, intel_crtc->config);
- }
for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->pre_enable)
@@ -7185,51 +7202,6 @@ static void chv_compute_dpll(struct intel_crtc *crtc,
(pipe_config->pixel_multiplier - 1) <<
DPLL_MD_UDI_MULTIPLIER_SHIFT;
}
-static void vlv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- enum pipe pipe = crtc->pipe;
-
- /* Enable Refclk */
- I915_WRITE(DPLL(pipe),
- pipe_config->dpll_hw_state.dpll &
- ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
-
- /* No need to actually set up the DPLL with DSI */
- if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
- return;
-
- vlv_phy_prepare_pll(crtc, pipe_config->dpll.n,
- pipe_config->dpll.m1, pipe_config->dpll.m2,
- pipe_config->dpll.p1, pipe_config->dpll.p2,
- pipe_config->port_clock,
- pipe_config->has_dp_encoder);
-
-}
-
-static void chv_prepare_pll(struct intel_crtc *crtc,
- const struct intel_crtc_state *pipe_config)
-{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = dev->dev_private;
- enum pipe pipe = crtc->pipe;
-
- /* Enable Refclk and SSC */
- I915_WRITE(DPLL(pipe),
- pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
-
- /* No need to actually set up the DPLL with DSI */
- if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
- return;
-
- chv_phy_prepare_pll(crtc, pipe_config->dpll.n,
- pipe_config->dpll.m1, pipe_config->dpll.m2,
- pipe_config->dpll.p1, pipe_config->dpll.p2,
- pipe_config->dpll.vco);
-}
-
/**
* vlv_force_pll_on - forcibly enable just the PLL
* @dev_priv: i915 private structure
@@ -7257,11 +7229,9 @@ int vlv_force_pll_on(struct drm_device *dev, enum pipe
pipe,
if (IS_CHERRYVIEW(dev)) {
chv_compute_dpll(crtc, pipe_config);
- chv_prepare_pll(crtc, pipe_config);
chv_enable_pll(crtc, pipe_config);
} else {
vlv_compute_dpll(crtc, pipe_config);
- vlv_prepare_pll(crtc, pipe_config);
vlv_enable_pll(crtc, pipe_config);
}
--
2.5.5
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