On Thu, Jul 28, 2016 at 04:23:42PM +0100, Dave Gordon wrote: > On 25/07/16 08:44, Chris Wilson wrote: > >As GEN6+ is now a simple variant on the basic breadcrumbs + tail write, > >reuse the common code. > > > >Signed-off-by: Chris Wilson <[email protected]> > >Reviewed-by: Joonas Lahtinen <[email protected]> > >--- > > drivers/gpu/drm/i915/intel_ringbuffer.c | 74 > > +++++++++++++-------------------- > > 1 file changed, 30 insertions(+), 44 deletions(-) > > > >diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > >b/drivers/gpu/drm/i915/intel_ringbuffer.c > >index 68df689a9d1e..a42d878009e6 100644 > >--- a/drivers/gpu/drm/i915/intel_ringbuffer.c > >+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > >@@ -1428,26 +1428,19 @@ static int gen6_signal(struct drm_i915_gem_request > >*signaller_req) > > return 0; > > } > > > >-/** > >- * gen6_emit_request - Update the semaphore mailbox registers > >- * > >- * @request - request to write to the ring > >- * > >- * Update the mailbox registers in the *other* rings with the current seqno. > >- * This acts like a signal in the canonical semaphore. > >- */ > >-static int gen6_emit_request(struct drm_i915_gem_request *req) > >+static void i9xx_submit_request(struct drm_i915_gem_request *request) > >+{ > >+ struct drm_i915_private *dev_priv = request->i915; > >+ > >+ I915_WRITE_TAIL(request->engine, > >+ request->tail % (request->ring->size - 1)); > >+} > > wrong mod-thing as previously noted - I don't know whether this is > already fixed up elsewhere.
You previously replied to altered patches with the recent changes undone in favour of introducing intel_ring_offset(). -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
