Hi Vitaly, kernel test robot noticed the following build warnings:
[auto build test WARNING on tnguy-net-queue/dev-queue] url: https://github.com/intel-lab-lkp/linux/commits/Vitaly-Lifshits/e1000e-introduce-new-MAC-type-for-Panther-Lake-PCH/20251223-175226 base: https://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue.git dev-queue patch link: https://lore.kernel.org/r/20251223095032.1379862-3-vitaly.lifshits%40intel.com patch subject: [Intel-wired-lan] [PATCH iwl-net v1 2/2] e1000e: clear DPG_EN after reset to avoid autonomous power-gating config: i386-randconfig-141-20251224 (https://download.01.org/0day-ci/archive/20251226/[email protected]/config) compiler: gcc-14 (Debian 14.2.0-19) 14.2.0 If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <[email protected]> | Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ smatch warnings: drivers/net/ethernet/intel/e1000e/ich8lan.c:4938 e1000_reset_hw_ich8lan() warn: inconsistent indenting vim +4938 drivers/net/ethernet/intel/e1000e/ich8lan.c 4823 4824 /** 4825 * e1000_reset_hw_ich8lan - Reset the hardware 4826 * @hw: pointer to the HW structure 4827 * 4828 * Does a full reset of the hardware which includes a reset of the PHY and 4829 * MAC. 4830 **/ 4831 static s32 e1000_reset_hw_ich8lan(struct e1000_hw *hw) 4832 { 4833 struct e1000_dev_spec_ich8lan *dev_spec = &hw->dev_spec.ich8lan; 4834 u16 kum_cfg; 4835 u32 ctrl, reg; 4836 s32 ret_val; 4837 4838 /* Prevent the PCI-E bus from sticking if there is no TLP connection 4839 * on the last TLP read/write transaction when MAC is reset. 4840 */ 4841 ret_val = e1000e_disable_pcie_master(hw); 4842 if (ret_val) 4843 e_dbg("PCI-E Master disable polling has failed.\n"); 4844 4845 e_dbg("Masking off all interrupts\n"); 4846 ew32(IMC, 0xffffffff); 4847 4848 /* Disable the Transmit and Receive units. Then delay to allow 4849 * any pending transactions to complete before we hit the MAC 4850 * with the global reset. 4851 */ 4852 ew32(RCTL, 0); 4853 ew32(TCTL, E1000_TCTL_PSP); 4854 e1e_flush(); 4855 4856 usleep_range(10000, 11000); 4857 4858 /* Workaround for ICH8 bit corruption issue in FIFO memory */ 4859 if (hw->mac.type == e1000_ich8lan) { 4860 /* Set Tx and Rx buffer allocation to 8k apiece. */ 4861 ew32(PBA, E1000_PBA_8K); 4862 /* Set Packet Buffer Size to 16k. */ 4863 ew32(PBS, E1000_PBS_16K); 4864 } 4865 4866 if (hw->mac.type == e1000_pchlan) { 4867 /* Save the NVM K1 bit setting */ 4868 ret_val = e1000_read_nvm(hw, E1000_NVM_K1_CONFIG, 1, &kum_cfg); 4869 if (ret_val) 4870 return ret_val; 4871 4872 if (kum_cfg & E1000_NVM_K1_ENABLE) 4873 dev_spec->nvm_k1_enabled = true; 4874 else 4875 dev_spec->nvm_k1_enabled = false; 4876 } 4877 4878 ctrl = er32(CTRL); 4879 4880 if (!hw->phy.ops.check_reset_block(hw)) { 4881 /* Full-chip reset requires MAC and PHY reset at the same 4882 * time to make sure the interface between MAC and the 4883 * external PHY is reset. 4884 */ 4885 ctrl |= E1000_CTRL_PHY_RST; 4886 4887 /* Gate automatic PHY configuration by hardware on 4888 * non-managed 82579 4889 */ 4890 if ((hw->mac.type == e1000_pch2lan) && 4891 !(er32(FWSM) & E1000_ICH_FWSM_FW_VALID)) 4892 e1000_gate_hw_phy_config_ich8lan(hw, true); 4893 } 4894 ret_val = e1000_acquire_swflag_ich8lan(hw); 4895 e_dbg("Issuing a global reset to ich8lan\n"); 4896 ew32(CTRL, (ctrl | E1000_CTRL_RST)); 4897 /* cannot issue a flush here because it hangs the hardware */ 4898 msleep(20); 4899 4900 /* Set Phy Config Counter to 50msec */ 4901 if (hw->mac.type == e1000_pch2lan) { 4902 reg = er32(FEXTNVM3); 4903 reg &= ~E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK; 4904 reg |= E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC; 4905 ew32(FEXTNVM3, reg); 4906 } 4907 4908 if (!ret_val) 4909 clear_bit(__E1000_ACCESS_SHARED_RESOURCE, &hw->adapter->state); 4910 4911 if (ctrl & E1000_CTRL_PHY_RST) { 4912 ret_val = hw->phy.ops.get_cfg_done(hw); 4913 if (ret_val) 4914 return ret_val; 4915 4916 ret_val = e1000_post_phy_reset_ich8lan(hw); 4917 if (ret_val) 4918 return ret_val; 4919 } 4920 4921 /* For PCH, this write will make sure that any noise 4922 * will be detected as a CRC error and be dropped rather than show up 4923 * as a bad packet to the DMA engine. 4924 */ 4925 if (hw->mac.type == e1000_pchlan) 4926 ew32(CRC_OFFSET, 0x65656565); 4927 4928 ew32(IMC, 0xffffffff); 4929 er32(ICR); 4930 4931 reg = er32(KABGTXD); 4932 reg |= E1000_KABGTXD_BGSQLBIAS; 4933 ew32(KABGTXD, reg); 4934 4935 /* The reset value of DPG_EN bit was changed to 1 4936 * clear it to avoid unexpected autonomous power-gating 4937 */ > 4938 if (hw->mac.type >= e1000_pch_ptp) { 4939 reg = er32(CTRL_EXT); 4940 reg &= ~E1000_CTRL_EXT; 4941 ew32(CTRL_EXT, reg); 4942 } 4943 4944 return 0; 4945 } 4946 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki
