Take this burden from the hypervisor where we have no easy way to
perform this flush. Currently the hypervisor does an undirected D-cache
flush by set/way which has a lot of problems and does not cover system
caches, e.g.
CC: Marc Zyngier <marc.zyng...@arm.com>
CC: Mark Rutland <mark.rutl...@arm.com>
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
---
driver/cell.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/driver/cell.c b/driver/cell.c
index 8a9ae26..8c4c0d8 100644
--- a/driver/cell.c
+++ b/driver/cell.c
@@ -309,13 +309,18 @@ static int load_image(struct cell *cell,
image.size))
err = -EFAULT;
/*
- * ARMv8 requires to clean D-cache and invalidate I-cache for memory
- * containing new instructions. On x86 this is a NOP. On ARMv7 the
- * firmware does its own cache maintenance, so it is an
- * extraneous (but harmless) flush.
+ * ARMv7 and ARMv8 require to clean D-cache and invalidate I-cache for
+ * memory containing new instructions. On x86 this is a NOP.
*/
flush_icache_range((unsigned long)(image_mem + page_offs),
(unsigned long)(image_mem + page_offs) + image.size);
+#ifdef CONFIG_ARM
+ /*
+ * ARMv7 requires to flush the written code and data out of D-cache to
+ * allow the guest starting off with caches disabled.
+ */
+ __cpuc_flush_dcache_area(image_mem + page_offs, image.size);
+#endif
vunmap(image_mem);
--
2.1.4
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