In the attempt to reduce the mapping effort on AArch64, HSR was called
ESR_EL2, like on AArch64. Also all related constants where prefixed with
ESR. This is only confusing when looking at the 32-bit spec. As arm64
will come with its own constants anyway, clean up the misleading names
on arm.
Signed-off-by: Jan Kiszka <jan.kis...@siemens.com>
---
hypervisor/arch/arm/include/asm/processor.h | 50 +++++++++++++--------------
hypervisor/arch/arm/include/asm/sysregs.h | 1 +
hypervisor/arch/arm/include/asm/traps.h | 2 +-
hypervisor/arch/arm/mmio.c | 2 +-
hypervisor/arch/arm/traps.c | 52 ++++++++++++++---------------
5 files changed, 54 insertions(+), 53 deletions(-)
diff --git a/hypervisor/arch/arm/include/asm/processor.h
b/hypervisor/arch/arm/include/asm/processor.h
index 907a28e..9be4362 100644
--- a/hypervisor/arch/arm/include/asm/processor.h
+++ b/hypervisor/arch/arm/include/asm/processor.h
@@ -115,35 +115,35 @@
#define PAR_ATTR_MASK 0xff
/* exception class */
-#define ESR_EC_SHIFT 26
-#define ESR_EC(hsr) ((hsr) >> ESR_EC_SHIFT & 0x3f)
+#define HSR_EC_SHIFT 26
+#define HSR_EC(hsr) ((hsr) >> HSR_EC_SHIFT & 0x3f)
/* instruction length */
-#define ESR_IL_SHIFT 25
-#define ESR_IL(hsr) ((hsr) >> ESR_IL_SHIFT & 0x1)
+#define HSR_IL_SHIFT 25
+#define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1)
/* Instruction specific */
-#define ESR_ICC_MASK 0x1ffffff
-#define ESR_ICC(hsr) ((hsr) & ESR_ICC_MASK)
+#define HSR_ICC_MASK 0x1ffffff
+#define HSR_ICC(hsr) ((hsr) & HSR_ICC_MASK)
/* Exception classes values */
-#define ESR_EC_UNK 0x00
-#define ESR_EC_WFI 0x01
-#define ESR_EC_CP15_32 0x03
-#define ESR_EC_CP15_64 0x04
-#define ESR_EC_CP14_32 0x05
-#define ESR_EC_CP14_LC 0x06
-#define ESR_EC_HCPTR 0x07
-#define ESR_EC_CP10 0x08
-#define ESR_EC_CP14_64 0x0c
-#define ESR_EC_SVC_HYP 0x11
-#define ESR_EC_HVC 0x12
-#define ESR_EC_SMC 0x13
-#define ESR_EC_IABT 0x20
-#define ESR_EC_IABT_HYP 0x21
-#define ESR_EC_PCALIGN 0x22
-#define ESR_EC_DABT 0x24
-#define ESR_EC_DABT_HYP 0x25
+#define HSR_EC_UNK 0x00
+#define HSR_EC_WFI 0x01
+#define HSR_EC_CP15_32 0x03
+#define HSR_EC_CP15_64 0x04
+#define HSR_EC_CP14_32 0x05
+#define HSR_EC_CP14_LC 0x06
+#define HSR_EC_HCPTR 0x07
+#define HSR_EC_CP10 0x08
+#define HSR_EC_CP14_64 0x0c
+#define HSR_EC_SVC_HYP 0x11
+#define HSR_EC_HVC 0x12
+#define HSR_EC_SMC 0x13
+#define HSR_EC_IABT 0x20
+#define HSR_EC_IABT_HYP 0x21
+#define HSR_EC_PCALIGN 0x22
+#define HSR_EC_DABT 0x24
+#define HSR_EC_DABT_HYP 0x25
/* Condition code */
-#define ESR_ICC_CV_BIT (1 << 24)
-#define ESR_ICC_COND(icc) ((icc) >> 20 & 0xf)
+#define HSR_ICC_CV_BIT (1 << 24)
+#define HSR_ICC_COND(icc) ((icc) >> 20 & 0xf)
#define EXIT_REASON_UNDEF 0x1
#define EXIT_REASON_HVC 0x2
diff --git a/hypervisor/arch/arm/include/asm/sysregs.h
b/hypervisor/arch/arm/include/asm/sysregs.h
index 83b5cff..c503dd6 100644
--- a/hypervisor/arch/arm/include/asm/sysregs.h
+++ b/hypervisor/arch/arm/include/asm/sysregs.h
@@ -43,6 +43,7 @@
#define VMPIDR_EL2 SYSREG_32(4, c0, c0, 5)
#define SCTLR_EL2 SYSREG_32(4, c1, c0, 0)
#define ESR_EL2 SYSREG_32(4, c5, c2, 0)
+#define HSR ESR_EL2 /* AArch32 name */
#define TPIDR_EL2 SYSREG_32(4, c13, c0, 2)
#define TTBR0_EL2 SYSREG_64(4, c2)
#define TCR_EL2 SYSREG_32(4, c2, c0, 2)
diff --git a/hypervisor/arch/arm/include/asm/traps.h
b/hypervisor/arch/arm/include/asm/traps.h
index 5d414ef..1364eef 100644
--- a/hypervisor/arch/arm/include/asm/traps.h
+++ b/hypervisor/arch/arm/include/asm/traps.h
@@ -28,7 +28,7 @@ enum trap_return {
struct trap_context {
unsigned long *regs;
- u32 esr;
+ u32 hsr;
u32 cpsr;
u32 pc;
};
diff --git a/hypervisor/arch/arm/mmio.c b/hypervisor/arch/arm/mmio.c
index 1098e8d..6b72f3e 100644
--- a/hypervisor/arch/arm/mmio.c
+++ b/hypervisor/arch/arm/mmio.c
@@ -68,7 +68,7 @@ int arch_handle_dabt(struct trap_context *ctx)
unsigned long hpfar;
unsigned long hdfar;
/* Decode the syndrome fields */
- u32 icc = ESR_ICC(ctx->esr);
+ u32 icc = HSR_ICC(ctx->hsr);
u32 isv = icc >> 24;
u32 sas = icc >> 22 & 0x3;
u32 sse = icc >> 21 & 0x1;
diff --git a/hypervisor/arch/arm/traps.c b/hypervisor/arch/arm/traps.c
index ae0990f..5723f05 100644
--- a/hypervisor/arch/arm/traps.c
+++ b/hypervisor/arch/arm/traps.c
@@ -48,11 +48,11 @@ static const unsigned short cc_map[16] = {
0 /* NV */
};
-/* Check condition field either from ESR or from SPSR in thumb mode */
+/* Check condition field either from HSR or from SPSR in thumb mode */
static bool arch_failed_condition(struct trap_context *ctx)
{
- u32 class = ESR_EC(ctx->esr);
- u32 icc = ESR_ICC(ctx->esr);
+ u32 class = HSR_EC(ctx->hsr);
+ u32 icc = HSR_ICC(ctx->hsr);
u32 cpsr = ctx->cpsr;
u32 flags = cpsr >> 28;
u32 cond;
@@ -64,8 +64,8 @@ static bool arch_failed_condition(struct trap_context *ctx)
return false;
/* Is condition field valid? */
- if (icc & ESR_ICC_CV_BIT) {
- cond = ESR_ICC_COND(icc);
+ if (icc & HSR_ICC_CV_BIT) {
+ cond = HSR_ICC_COND(icc);
} else {
/* This can happen in Thumb mode: examine IT state. */
unsigned long it = PSR_IT(cpsr);
@@ -118,7 +118,7 @@ static void arch_advance_itstate(struct trap_context *ctx)
void arch_skip_instruction(struct trap_context *ctx)
{
- u32 instruction_length = ESR_IL(ctx->esr);
+ u32 instruction_length = HSR_IL(ctx->hsr);
ctx->pc += (instruction_length ? 4 : 2);
arch_advance_itstate(ctx);
@@ -194,8 +194,8 @@ static void dump_guest_regs(struct trap_context *ctx)
u8 reg;
unsigned long reg_val;
- panic_printk("pc=0x%08x cpsr=0x%08x esr=0x%08x\n", ctx->pc, ctx->cpsr,
- ctx->esr);
+ panic_printk("pc=0x%08x cpsr=0x%08x hsr=0x%08x\n", ctx->pc, ctx->cpsr,
+ ctx->hsr);
for (reg = 0; reg < 15; reg++) {
access_cell_reg(ctx, reg, ®_val, true);
panic_printk("r%d=0x%08x ", reg, reg_val);
@@ -233,12 +233,12 @@ static int arch_handle_hvc(struct trap_context *ctx)
static int arch_handle_cp15_32(struct trap_context *ctx)
{
- u32 opc2 = ctx->esr >> 17 & 0x7;
- u32 opc1 = ctx->esr >> 14 & 0x7;
- u32 crn = ctx->esr >> 10 & 0xf;
- u32 rt = ctx->esr >> 5 & 0xf;
- u32 crm = ctx->esr >> 1 & 0xf;
- u32 read = ctx->esr & 1;
+ u32 opc2 = ctx->hsr >> 17 & 0x7;
+ u32 opc1 = ctx->hsr >> 14 & 0x7;
+ u32 crn = ctx->hsr >> 10 & 0xf;
+ u32 rt = ctx->hsr >> 5 & 0xf;
+ u32 crm = ctx->hsr >> 1 & 0xf;
+ u32 read = ctx->hsr & 1;
if (opc1 == 0 && crn == 1 && crm == 0 && opc2 == 1) {
/* Do not let the guest disable coherency by writing ACTLR... */
@@ -258,11 +258,11 @@ static int arch_handle_cp15_32(struct trap_context *ctx)
static int arch_handle_cp15_64(struct trap_context *ctx)
{
unsigned long rt_val, rt2_val;
- u32 opc1 = ctx->esr >> 16 & 0x7;
- u32 rt2 = ctx->esr >> 10 & 0xf;
- u32 rt = ctx->esr >> 5 & 0xf;
- u32 crm = ctx->esr >> 1 & 0xf;
- u32 read = ctx->esr & 1;
+ u32 opc1 = ctx->hsr >> 16 & 0x7;
+ u32 rt2 = ctx->hsr >> 10 & 0xf;
+ u32 rt = ctx->hsr >> 5 & 0xf;
+ u32 crm = ctx->hsr >> 1 & 0xf;
+ u32 read = ctx->hsr & 1;
if (!read) {
access_cell_reg(ctx, rt, &rt_val, true);
@@ -287,11 +287,11 @@ static int arch_handle_cp15_64(struct trap_context *ctx)
static const trap_handler trap_handlers[38] =
{
- [ESR_EC_CP15_32] = arch_handle_cp15_32,
- [ESR_EC_CP15_64] = arch_handle_cp15_64,
- [ESR_EC_HVC] = arch_handle_hvc,
- [ESR_EC_SMC] = arch_handle_smc,
- [ESR_EC_DABT] = arch_handle_dabt,
+ [HSR_EC_CP15_32] = arch_handle_cp15_32,
+ [HSR_EC_CP15_64] = arch_handle_cp15_64,
+ [HSR_EC_HVC] = arch_handle_hvc,
+ [HSR_EC_SMC] = arch_handle_smc,
+ [HSR_EC_DABT] = arch_handle_dabt,
};
void arch_handle_trap(struct per_cpu *cpu_data, struct registers *guest_regs)
@@ -302,8 +302,8 @@ void arch_handle_trap(struct per_cpu *cpu_data, struct
registers *guest_regs)
arm_read_banked_reg(ELR_hyp, ctx.pc);
arm_read_banked_reg(SPSR_hyp, ctx.cpsr);
- arm_read_sysreg(ESR_EL2, ctx.esr);
- exception_class = ESR_EC(ctx.esr);
+ arm_read_sysreg(HSR, ctx.hsr);
+ exception_class = HSR_EC(ctx.hsr);
ctx.regs = guest_regs->usr;
/*
--
2.1.4
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