No functional changes.
Signed-off-by: Jan Kiszka <[email protected]>
---
hypervisor/arch/arm64/entry.S | 4 ++--
hypervisor/arch/arm64/setup.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hypervisor/arch/arm64/entry.S b/hypervisor/arch/arm64/entry.S
index 96a69a0..ab29f39 100644
--- a/hypervisor/arch/arm64/entry.S
+++ b/hypervisor/arch/arm64/entry.S
@@ -52,7 +52,7 @@ arch_entry:
* guests, which can execute 'dc isw' (data or unified Cache line
* Invalidate by Set/Way) because when virtualization is enabled
* (HCR_EL2.VM == 1) then HW automatically upgrade 'dc isw' to
- * 'dc cisw' (Clean + Invallidate). Executing Clean operation before
+ * 'dc cisw' (Clean + Invalidate). Executing Clean operation before
* Invalidate is safe in guests.
*/
@@ -170,7 +170,7 @@ enable_mmu_el2:
* Shareable domain is expected to be the set of PEs controlled by
* a single hypervisor or operating system." (see p. 93 of ARM ARM)
* We should think what hw configuration we support by one instance of
- * the hypervisor and choose Inner or Outter sharable domain.
+ * the hypervisor and choose Inner or Outer sharable domain.
*/
ldr x1, =(T0SZ(48) | (TCR_RGN_WB_WA << TCR_IRGN0_SHIFT) \
| (TCR_RGN_WB_WA << TCR_ORGN0_SHIFT) \
diff --git a/hypervisor/arch/arm64/setup.c b/hypervisor/arch/arm64/setup.c
index 8d5bd38..c2ccee6 100644
--- a/hypervisor/arch/arm64/setup.c
+++ b/hypervisor/arch/arm64/setup.c
@@ -109,7 +109,7 @@ void arch_shutdown_self(struct per_cpu *cpu_data)
arm_write_sysreg(VTTBR_EL2, 0);
/* we will restore the root cell state with the MMU turned off,
- * so we need to make sure it has been commited to memory */
+ * so we need to make sure it has been committed to memory */
arch_paging_flush_cpu_caches(guest_regs(cpu_data),
sizeof(struct registers));
dsb(ish);
--
2.1.4
--
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