Thanks Jan.
It is working now. the irqchip in the non-root cell was missing.
I added the following to the non-root cell:
struct jailhouse_irqchip irqchips[1];
...
.vpci_irq_base = 140-32
...
.irqchips = {
/* GIC */ {
.address = 0xf9010000,
.pin_base = 32,
.pin_bitmap = {
1 << (54 - 32),
0,
0,
(1 << (140 - 128)) | (1 << (142 - 128))
},
},
},
I attached here both configurations for those that want to use ivhsmem
interrupts in arm64. I would be happy to help to incorporate this working demo
into the master branch.
Giovani
> On 2018-04-17 15:17, Giovani Gracioli wrote:
> > It is not completely the same configurations, one is the root-cell and
> > another one is a bare-metal cell based on the gic-demo. I attached both
> > here.
> >
> > I believe the Linux program is correct, because I can see the number of
> > interrupts increasing by outputting /proc/interrupts. It basically maps
> > 0xfc100000 using mmap and then writes 1 to mapped_adress + 3.
> >
>
> Root cell and non-root cell are still sharing interrupts /wrt the
> virtual pci host controller and ivshmem. Just derive your inmate config
> from configs/arm64/zynqmp-zcu102-linux-demo[-2].c, those work.
>
> Jan
>
> >> On 2018-04-16 23:53, Giovani Gracioli wrote:
> >>> I instrumented the code with several prints.
> >>>
> >>> When I start the bare-metal cell, I can see that an interrupt from CPU 3
> >>> is issued and handled by CPU 0:
> >>>
> >>> Started cell "gic-demo-ivshmem"
> >>> ivshmem_register_mmio() mmio->address = 8, mmio->is_write = 0, current
> >>> cpu = 3
> >>> ivshmem_register_mmio() mmio->address = 0, mmio->is_write = 1, current
> >>> cpu = 3
> >>> arch_ivshmem_update_intx(ive=0x0000ffffc02450a0),
> >>> device->info->num_msix_vectors = 0, ctrl eg intx enable = 1
> >>> ivshmem_register_mmio() mmio->address = 12, mmio->is_write = 1, current
> >>> cpu = 3
> >>> @@@@@ ivshmem_remote_interrupt() ive->remote: 0x0000ffffc0245000, current
> >>> cpu = 3
> >>> arch_ivshmem_trigger_interrupt(ive:0x0000ffffc0245000), irq_id:136,
> >>> current cpu = 3
> >>> irqchip_set_pending(), local_injection = 0, sender (current cpu) = 3
> >>> irqchip_set_pending() -> inside if(!cpu_data)
> >>> irqchip_handle_irq(cpu_data:0x0000ffffc021d000, irq_id:136),
> >>> is_sgi(irq_id) = 0
> >>> irqchip_handle_irq() this_cpu_data() = 0x0000ffffc021d000, current cpu 0,
> >>> cpu_data->cpu_id = 0
> >>> arch_handle_phys_irq calling
> >>> irqchip_set_pending(cpu_data=0x0000ffffc021d000, irqn=136), cpu_id = 0
> >>> irqchip_set_pending(), local_injection = 1, sender (current cpu) = 0
> >>> irqchip_set_pending() -> just return after irqchip.inject_irq,
> >>> cpu_data->cpu_id = 0
> >>> irqchip_set_pending(), local_injection = 1, sender (current cpu) = 0
> >>> irqchip_set_pending() -> just return after irqchip.inject_irq,
> >>> cpu_data->cpu_id = 0
> >>>
> >>> When I run the program to generate an interrupt from Linux, I got the
> >>> following output:
> >>>
> >>> /dev/mem opened.
> >>> Memory mapped at address 0x7f988f2000.
> >>> Writing 1 to 0x7f988f200c
> >>> ivshmem_register_mmio() mmio->address = 12, mmio->is_write = 1, current
> >>> cpu = 1
> >>> @@@@@ ivshmem_remote_interrupt() ive->remote: 0x0000ffffc02450a0, current
> >>> cpu = 1
> >>> arch_ivshmem_trigger_interrupt(ive:0x0000ffffc02450a0), irq_id:136,
> >>> current cpu = 1
> >>> irqchip_set_pending(), local_injection = 0, sender (current cpu) = 1
> >>> irqchip_set_pending() -> inside if(!cpu_data)
> >>> irqchip_handle_irq(cpu_data:0x0000ffffc021d000, irq_id:136),
> >>> is_sgi(irq_id) = 0
> >>> irqchip_handle_irq() this_cpu_data() = 0x0000ffffc021d000, current cpu 0,
> >>> cpu_data->cpu_id = 0
> >>> arch_handle_phys_irq calling
> >>> irqchip_set_pending(cpu_data=0x0000ffffc021d000, irqn=136), cpu_id = 0
> >>> irqchip_set_pending(), local_injection = 1, sender (current cpu) = 0
> >>> irqchip_set_pending() -> just return after irqchip.inject_irq,
> >>> cpu_data->cpu_id = 0
> >>> irqchip_handle_irq(cpu_data:0x0000ffffc021d000, irq_id:25),
> >>> is_sgi(irq_id) = 0
> >>> irqchip_handle_irq() this_cpu_data() = 0x0000ffffc021d000, current cpu 0,
> >>> cpu_data->cpu_id = 0
> >>> irqchip_set_pending(), local_injection = 1, sender (current cpu) = 0
> >>> irqchip_set_pending() -> just return after irqchip.inject_irq,
> >>> cpu_data->cpu_id = 0
> >>>
> >>> Seems that the connection between Linux (root-cell) and the bare-metal
> >>> one is not correct, but the other way around is fine. Why is that?
> >>
> >> Just to confirm my understanding: You have the same cell configurations,
> >> just switching the binary executed in the non-root cell between Linux
> >> and a bare-metal inmate, right?
> >>
> >> Is the root Linux programming the INTX_CTRL register properly (not part
> >> of your trace)?
> >>
> >> Jan
> >>
> >> --
> >> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> >> Corporate Competence Center Embedded Linux
> >
>
> --
> Siemens AG, Corporate Technology, CT RDA IOT SES-DE
> Corporate Competence Center Embedded Linux
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/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for Xilinx ZynqMP ZCU102 eval board
*
* Copyright (c) Siemens AG, 2016
*
* Authors:
* Jan Kiszka <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*
* Reservation via device tree: 0x800000000..0x83fffffff
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
struct {
struct jailhouse_system header;
__u64 cpus[1];
struct jailhouse_memory mem_regions[4];
struct jailhouse_irqchip irqchips[1];
struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
.header = {
.signature = JAILHOUSE_SYSTEM_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.hypervisor_memory = {
.phys_start = 0x800000000,
.size = 0x000400000,
},
.debug_console = {
.address = 0xff000000,
.size = 0x1000,
.flags = JAILHOUSE_CON1_TYPE_XUARTPS |
JAILHOUSE_CON1_ACCESS_MMIO |
JAILHOUSE_CON1_REGDIST_4 |
JAILHOUSE_CON2_TYPE_ROOTPAGE,
},
.platform_info = {
.pci_mmconfig_base = 0xfc000000,
.pci_mmconfig_end_bus = 0,
.pci_is_virtual = 1,
.arm = {
.gic_version = 2,
.gicd_base = 0xf9010000,
.gicc_base = 0xf902f000,
.gich_base = 0xf9040000,
.gicv_base = 0xf906f000,
.maintenance_irq = 25,
},
},
.root_cell = {
.name = "ZynqMP-ZCU102",
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.vpci_irq_base = 136-32,
},
},
.cpus = {
0xf,
},
.mem_regions = {
/* MMIO (permissive) */ {
.phys_start = 0xfd000000,
.virt_start = 0xfd000000,
.size = 0x03000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO,
},
/* RAM */ {
.phys_start = 0x0,
.virt_start = 0x0,
.size = 0x80000000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
/* RAM */ {
.phys_start = 0x800600000,
.virt_start = 0x800600000,
.size = 0x7fa00000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE,
},
/* IVSHMEM shared memory region for 00:00.0 */ {
.phys_start = 0x800400000,
.virt_start = 0x800400000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},
/* IVSHMEM shared memory region for 00:01.0 */ /*{
.phys_start = 0x800500000,
.virt_start = 0x800500000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE,
},*/
},
.irqchips = {
/* GIC */ {
.address = 0xf9010000,
.pin_base = 32,
.pin_bitmap = {
0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
},
},
},
.pci_devices = {
/* 00:00.0 */ {
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.shmem_region = 3,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
.num_msix_vectors = 0,
},
/* 00:01.0 */ /*{
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 1,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.shmem_region = 4,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
.num_msix_vectors = 0,
},*/
},
};
/*
* Jailhouse, a Linux-based partitioning hypervisor
*
* Configuration for gic-demo inmate on Xilinx ZynqMP ZCU102 eval board:
* 1 CPU, 64K RAM, 1 serial port
*
* Copyright (c) Siemens AG, 2016
*
* Authors:
* Jan Kiszka <[email protected]>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
*/
#include <jailhouse/types.h>
#include <jailhouse/cell-config.h>
#define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0])
struct {
struct jailhouse_cell_desc cell;
__u64 cpus[1];
struct jailhouse_memory mem_regions[3];
struct jailhouse_irqchip irqchips[1];
struct jailhouse_pci_device pci_devices[1];
} __attribute__((packed)) config = {
.cell = {
.signature = JAILHOUSE_CELL_DESC_SIGNATURE,
.revision = JAILHOUSE_CONFIG_REVISION,
.name = "gic-demo-ivshmem",
.flags = JAILHOUSE_CELL_PASSIVE_COMMREG,
.cpu_set_size = sizeof(config.cpus),
.num_memory_regions = ARRAY_SIZE(config.mem_regions),
.num_irqchips = ARRAY_SIZE(config.irqchips),
.num_pci_devices = ARRAY_SIZE(config.pci_devices),
.vpci_irq_base = 140-32,
},
.cpus = {
0x8,
},
.mem_regions = {
/* UART */ {
.phys_start = 0xff010000,
.virt_start = 0xff010000,
.size = 0x1000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED,
},
/* RAM */ {
.phys_start = 0x800600000,
.virt_start = 0,
.size = 0x00010000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE |
JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE,
},
/* IVSHMEM shared memory region for 00:00.0 */ {
.phys_start = 0x800400000,
.virt_start = 0x800400000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
},
/* IVSHMEM shared memory region for 00:01.0 */ //{
/* .phys_start = 0x800500000,
.virt_start = 0x800500000,
.size = 0x100000,
.flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED,
},*/
},
.irqchips = {
/* GIC */ {
.address = 0xf9010000,
.pin_base = 32,
.pin_bitmap = {
1 << (54 - 32),
0,
0,
(1 << (140 - 128)) | (1 << (142 - 128))
},
},
},
.pci_devices = {
/* 00:00.0 */ {
.type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 0,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.shmem_region = 2,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
.num_msix_vectors = 0,
},
/* 00:01.0 */ //{
/* .type = JAILHOUSE_PCI_TYPE_IVSHMEM,
.bdf = 1,
.bar_mask = {
0xffffff00, 0xffffffff, 0x00000000,
0x00000000, 0x00000000, 0x00000000,
},
.shmem_region = 3,
.shmem_protocol = JAILHOUSE_SHMEM_PROTO_UNDEFINED,
.num_msix_vectors = 0,
},*/
},
};
