On 28.02.19 20:35, João Reis wrote:
segunda-feira, 25 de Fevereiro de 2019 às 07:56:57 UTC, J. Kiszka escreveu:
On 25.02.19 00:52, João Reis wrote:
domingo, 24 de Fevereiro de 2019 às 09:47:34 UTC, Jan Kiszka escreveu:
On 23.02.19 18:32, João Reis wrote:
sábado, 23 de Fevereiro de 2019 às 10:29:41 UTC, Jan Kiszka escreveu:
On 22.02.19 15:10, João Reis wrote:
sexta-feira, 22 de Fevereiro de 2019 às 13:19:56 UTC, J. Kiszka escreveu:
Please always keep the list in CC ("reply-to-all").
I'm sorry, i forgot to cc to this group.
Also "jailhouse cell linux" does a "cell create" under the hood, but maybe there
is something subtly borken that only surfaces this way. I probable never tested
you pattern. Will do.
Ok, i'll be waiting for your test. Thank you for your availability.
All working fine - provided you issue the "cell create" in an ssh session,
rather than on the serial console. As the Linux cell will take away the UART
from the root cell, the latter approach will make the system appear as if it is
locked up.
Jan
Ok, that might be the problem. I was executing "cell create" on the serial
console, so probably that's why it is freezing.
Just have one question, in what does the linux cell, or .c file, differ from gic-demo
cell in a sense that one (linux cell) takes away the UART from root cell and the other
(gic-demo cell) doesn't? (i suppose this because in gic-demo cell i can still write to
serial console after "create cell" command)
The gic-demo shares the UART with the root cell in output-only mode. In
contrast, the Linux non-root cell also uses the UART as input, and that mode
cannot be shared.
Jan
But both gic-demo and linux cells share the same flags in UART memory region
(JAILHOUSE_MEM_READ, JAILHOUSE_MEM_WRITE, JAILHOUSE_MEM_IO,
JAILHOUSE_MEM_ROOTSHARED). Is there another configuration that allows linux
cell to use UART as input? Could you tell me where it is?
Compare the irqchip settings.
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
I tried to search what irqchip pin bitmap means in Ultrascale+ TRM but it only refers to
that address as GICD responsible for Display Controller, so i proceeded to search in Arm
Generic Interrupt Controller Architecture Specification and the registers on base address
32 are referred as "IMPLEMENTATION DEFINED registers".
On ARM, the jailhouse_irqchip controls access to external interrupt lines
starting from interrupt 32 onward (but using interrupt 0 as basis, i.e.
including SGIs and PPIs into the enumeration).
If i want the linux cell to start outputing and inputting on UART0 instead of
UART1 (to not collide with root cell), do i only need to change .console
address field and UART .phys_start address to 0xff000000??
For Linux, you need to change the cell configuration (assigned memory region and
interrupt controller pin) and the device tree. The .console information is only
for bare metal inmates and other RTOS guests that interpret those bits.
Jan
--
Siemens AG, Corporate Technology, CT RDA IOT SES-DE
Corporate Competence Center Embedded Linux
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