terça-feira, 5 de Março de 2019 às 09:32:12 UTC, J. Kiszka escreveu: > On 04.03.19 15:31, João Reis wrote: > > sexta-feira, 1 de Março de 2019 às 15:42:04 UTC, J. Kiszka escreveu: > >> On 01.03.19 16:04, João Reis wrote: > >>> As i didn't find documentation that supports bit by bit information of > >>> GICD registers (as you can see by gicd_registers.png), i have to ask you > >>> what do i change in .irqchips field. > >>> > >> > >> You do not need to look at the GICD registers in order to assign > >> interrupts to > >> different cells. That's what Jailhouse is doing for you. All you need to > >> know is > >> which interrupt (SPI number + 32) each device is using. Then you can turn > >> on > >> access to that by setting the corresponding bit in the irqchip > >> configuration of > >> Jailhouse. > >> > >>> Where do i insert the modified inmate-zynqmp.dtb file? When i issue "cell > >>> create"? > >>> > >> > >> You pass that dtb to "cell linux". > >> > >> Jan > >> > >> -- > >> Siemens AG, Corporate Technology, CT RDA IOT SES-DE > >> Corporate Competence Center Embedded Linux > > > > I don't want to load linux on a non-root cell, i just want to create a > > non-root cell that shares memory with root cell, but that non-root cell > > must use UART1 and root cell UART0. So i suppose i must not issue "cell > > linux" because that command, besides creating a cell, loads linux on that > > cell. > > > > Then you do not need to touch a device tree but the cell config (.console) > and > use an inmate that evaluates that (like our demo inmates). Note that our > inmates > do not use the UART IRQ, they just poll the device for being able to write to > the console. > > Jan > > -- > Siemens AG, Corporate Technology, CT RDA IOT SES-DE > Corporate Competence Center Embedded Linux
Ok, so i've changed the non-root cell to output and input to UART0, can you tell me if the changes are correct? I still can't see anything on UART0. -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
/* * Jailhouse, a Linux-based partitioning hypervisor * * Configuration for linux-demo inmate on Avnet Ultra96 board: * 2 CPUs, 128M RAM, serial port 2 * * Copyright (c) Siemens AG, 2014-2019 * * Authors: * Jan Kiszka <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. */ #include <jailhouse/types.h> #include <jailhouse/cell-config.h> #define ARRAY_SIZE(a) sizeof(a) / sizeof(a[0]) struct { struct jailhouse_cell_desc cell; __u64 cpus[1]; struct jailhouse_memory mem_regions[5]; struct jailhouse_irqchip irqchips[1]; struct jailhouse_pci_device pci_devices[1]; } __attribute__((packed)) config = { .cell = { .signature = JAILHOUSE_CELL_DESC_SIGNATURE, .revision = JAILHOUSE_CONFIG_REVISION, .name = "Ultra96-linux-demo", .flags = JAILHOUSE_CELL_PASSIVE_COMMREG | JAILHOUSE_CELL_VIRTUAL_CONSOLE_ACTIVE, .cpu_set_size = sizeof(config.cpus), .num_memory_regions = ARRAY_SIZE(config.mem_regions), .num_irqchips = ARRAY_SIZE(config.irqchips), .num_pci_devices = ARRAY_SIZE(config.pci_devices), .vpci_irq_base = 140-32, .console = { //.address = 0xff010000, /*UART1*/ .address = 0xff000000, /*UART0*/ .type= JAILHOUSE_CON_TYPE_XUARTPS, .flags = JAILHOUSE_CON_ACCESS_MMIO | JAILHOUSE_CON_REGDIST_4, }, }, .cpus = { 0xc, }, .mem_regions = { /* UART */ { /*.phys_start = 0xff010000, .virt_start = 0xff010000,*/ .phys_start = 0xff000000, .virt_start = 0xff000000, .size = 0x1000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_IO | JAILHOUSE_MEM_ROOTSHARED, }, /* RAM */ { .phys_start = 0x7bef0000, .virt_start = 0, .size = 0x10000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_LOADABLE, }, /* RAM */ { .phys_start = 0x74000000, .virt_start = 0x74000000, .size = 0x7ef0000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_EXECUTE | JAILHOUSE_MEM_DMA | JAILHOUSE_MEM_LOADABLE, }, /* IVSHMEM shared memory region */ { .phys_start = 0x7bf00000, .virt_start = 0x7bf00000, .size = 0x100000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_ROOTSHARED, }, /* communication region */ { .virt_start = 0x80000000, .size = 0x00001000, .flags = JAILHOUSE_MEM_READ | JAILHOUSE_MEM_WRITE | JAILHOUSE_MEM_COMM_REGION, }, }, .irqchips = { /* GIC */ { .address = 0xf9010000, /* GICD base address - Display controller */ .pin_base = 32, /* The first irqchip starts at .pin_base=32 as the first 32 interrupts are reserved for SGIs and PPIs. */ .pin_bitmap = { //1 << (54 - 32), 1 << (53 - 32), // cat /proc/interrupts interrupt da UART0 0, 0, (1 << (140 - 128)) | (1 << (142 - 128)) //PL to PS interrupt signals 8 to 15. }, }, }, .pci_devices = { /* 00:00.0 */ { .type = JAILHOUSE_PCI_TYPE_IVSHMEM, .bdf = 0 << 3, .bar_mask = { 0xffffff00, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, }, .shmem_region = 3, .shmem_protocol = JAILHOUSE_SHMEM_PROTO_VETH, }, }, };
