Add RISC-V cell-specific fields. Unlike ARM, for example, the PLIC doesn't support hardware injection of external IRQs. So we need to do it in software, sigh...
Prepare the fields that are needed for software injection. The irq_bitmap, just like on ARM, denotes physical IRQs that the cell is allowed to manage. Signed-off-by: Ralf Ramsauer <[email protected]> --- hypervisor/arch/riscv/include/asm/cell.h | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hypervisor/arch/riscv/include/asm/cell.h b/hypervisor/arch/riscv/include/asm/cell.h index 63ba43ce..58412414 100644 --- a/hypervisor/arch/riscv/include/asm/cell.h +++ b/hypervisor/arch/riscv/include/asm/cell.h @@ -2,9 +2,11 @@ * Jailhouse, a Linux-based partitioning hypervisor * * Copyright (c) Siemens AG, 2020 + * Copyright (c) OTH Regensburg, 2022 * * Authors: - * Jan Kiszka <[email protected]> + * Konrad Schwarz <[email protected]> + * Ralf Ramsauer <[email protected]> * * This work is licensed under the terms of the GNU GPL, version 2. See * the COPYING file in the top-level directory. @@ -13,12 +15,14 @@ #ifndef _JAILHOUSE_ASM_CELL_H #define _JAILHOUSE_ASM_CELL_H +#include <jailhouse/paging.h> #include <jailhouse/types.h> - -// this shouldn't be here -#include <jailhouse/cell-config.h> +#include <asm/plic.h> struct arch_cell { + struct paging_structures mm; + + u32 irq_bitmap[PLIC_MAX_IRQS / (sizeof(u32) * 8)]; }; #endif /* !_JAILHOUSE_ASM_CELL_H */ -- 2.36.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/20220627132905.4338-13-ralf.ramsauer%40oth-regensburg.de.
