It's pretty easy on RISC-V: All platform specific confi information that we need is the PLIC.
Base/size fields are obvious, max_irq defines the highest possible IRQ on the controller. max_priority the highest possible priority of an IRQ. hart_to_context is a map that maps physical HART IDs to PLIC Contexts. On regular RISC-V platforms, M and S-Mode of a HART are assigned to one specific PLIC Context. For example: PLIC Ctx 0 -> Hart 0, M-Mode PLIC Ctx 1 -> Hart 0, S-Mode PLIC Ctx 2 -> Hart 1, M-Mode PLIC Ctx 3 -> Hart 1, S-Mode PLIC Ctx 4 -> Hart 2, M-Mode ... This is also how QEMU implements the PLIC. However, there are other implementations out there, like the NOEL-V. There, we have: PLIC Ctx 0 -> Hart 0, M-Mode PLIC Ctx 1 -> Hart 0, S-Mode PLIC Ctx 2 -> ? PLIC Ctx 3 -> ? PLIC Ctx 4 -> Hart 1, M-Mode PLIC Ctx 5 -> Hart 1, S-Mode PLIC Ctx 6 -> ? ... So we use the hart_to_context map to assign a hart to a Context ID. Signed-off-by: Ralf Ramsauer <[email protected]> --- include/jailhouse/cell-config.h | 11 ++++++++++- pyjailhouse/config_parser.py | 17 ++++++++++++++--- tools/jailhouse-config-check | 9 ++++++++- 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/include/jailhouse/cell-config.h b/include/jailhouse/cell-config.h index 124373d5..c90a649d 100644 --- a/include/jailhouse/cell-config.h +++ b/include/jailhouse/cell-config.h @@ -50,7 +50,7 @@ * Incremented on any layout or semantic change of system or cell config. * Also update formats and HEADER_REVISION in pyjailhouse/config_parser.py. */ -#define JAILHOUSE_CONFIG_REVISION 14 +#define JAILHOUSE_CONFIG_REVISION 15 #define JAILHOUSE_CELL_NAME_MAXLEN 31 @@ -357,6 +357,15 @@ struct jailhouse_system { u64 gicv_base; u64 gicr_base; } __attribute__((packed)) arm; + struct { + struct { + u64 base_address; + u32 size; + u16 max_irq; + u32 max_priority; + s16 hart_to_context[32]; + } __attribute__((packed)) plic; + } __attribute__((packed)) riscv; } __attribute__((packed)); } __attribute__((packed)) platform_info; struct jailhouse_cell_desc root_cell; diff --git a/pyjailhouse/config_parser.py b/pyjailhouse/config_parser.py index fc2158e1..37d8e039 100644 --- a/pyjailhouse/config_parser.py +++ b/pyjailhouse/config_parser.py @@ -19,7 +19,7 @@ import struct from .extendedenum import ExtendedEnum # Keep the whole file in sync with include/jailhouse/cell-config.h. -_CONFIG_REVISION = 14 +_CONFIG_REVISION = 15 def flag_str(enum_class, value, separator=' | '): @@ -245,6 +245,8 @@ class SystemConfig: _NUM_IOMMUS = 8 _ARCH_ARM_FORMAT = '=BB2xQQQQQ' _ARCH_X86_FORMAT = '=HBxIII28x' + _ARCH_RISCV_FORMAT = '=QIHI' + _ARCH_RISCV_FORMAT_HTC = '=32H' def __init__(self, data, arch): self.data = data @@ -294,8 +296,17 @@ class SystemConfig: self.x86_tsc_khz, self.x86_apic_khz) = \ struct.unpack_from(self._ARCH_X86_FORMAT, self.data[offs:]) - - offs += struct.calcsize(self._ARCH_ARM_FORMAT) + elif arch == 'riscv64': + (self.riscv_plic_base_address, + self.riscv_plic_size, + self.riscv_plic_max_irq, + self.riscv_plic_max_priority) = \ + self.riscv_plic_hart_to_context = \ + struct.unpack_from(self._ARCH_RISCV_FORMAT, self.data[offs:]) + self.riscv_plic_hart_to_context = \ + struct.unpack_from(self._ARCH_RISCV_FORMAT_HTC, self.data[offs:]) + offs += struct.calcsize(self._ARCH_RISCV_FORMAT) + offs += struct.calcsize(self._ARCH_RISCV_FORMAT_HTC) except struct.error: raise RuntimeError('Not a root cell configuration') diff --git a/tools/jailhouse-config-check b/tools/jailhouse-config-check index d6ea7079..13fd6ff7 100755 --- a/tools/jailhouse-config-check +++ b/tools/jailhouse-config-check @@ -61,9 +61,11 @@ if not arch: arch = 'arm' elif arch_str == 'aarch64': arch = 'arm64' + elif arch_str == 'riscv64': + arch = 'riscv64' else: arch = None -if not arch in ('x86', 'arm', 'arm64'): +if not arch in ('x86', 'arm', 'arm64', "riscv64"): print('Unsupported architecture', file=sys.stderr) exit(1) @@ -188,6 +190,11 @@ elif arch == 'x86': for irqchip in root_cell.irqchips: arch_resources.append(ResourceRegion(irqchip.address, 0x1000, "IOAPIC")) +elif arch in ('riscv64'): + arch_resources = [] + arch_resources.append(ResourceRegion(sysconfig.riscv_plic_base_address, + sysconfig.riscv_plic_size. "PLIC")) + for cell in cells: for mem in cell.memory_regions: idx = cell.memory_regions.index(mem) -- 2.36.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web visit https://groups.google.com/d/msgid/jailhouse-dev/20220627132905.4338-11-ralf.ramsauer%40oth-regensburg.de.
