Hi Albert,
[email protected] wrote: > While working on 18f devices, I noticed that all pin definitions point > to LAT registers, e.g. > > (18f4550.jal) > var volatile bit pin_B5 shared at LATB : 5 Sorry, I didn't read this carefully enough the first time and missed the real issue. I understand that all output pin/nibble/port operations should address the LATx register, while all input should address the pin/nibble/port. Do you agree? This has some impact on my dev2jal script with which the device files are generated. I'll prepare for the changes. Can I send you the result and have a look at it (or better test it) before committing it to Jallib? Would the device file for the 18F4550 be OK with you or which other 18F would you prefer? While we are at this subject: is there any need to use a shadow for the TRIS registers? I have built this in because I saw it somewhere else, but I doubt if this is necessary / useful. Regards, Rob. -- Rob Hamerling, Vianen, NL (http://www.robh.nl/) --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "jallib" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [email protected] For more options, visit this group at http://groups.google.com/group/jallib?hl=en -~----------~----~----~----~------~----~------~--~---
