Hi Matt,
mattschinkel wrote:
Rob, what will happen with these registers for timer0 on 18f, should I
open an issue? These aliases could be added to device files.
if target_cpu == PIC_16 then
alias option_reg_t0cs is t0con_t0cs
alias option_reg_psa is t0con_psa
alias option_reg_ps is t0con_t0ps
end if
My first reaction: "huh, why not the other way around"?
The 18Fs are much better structure/organized than the midrange and have
a T0CON register. So in my view a better option would be to do it like this:
if target_cpu == PIC_14 | target_cpu == PIC12 then
alias T0CON_CS is OPTION_REG_T0CS
alias T0CON_PSA is OPTION_REG_PSA
alias T0CON_PS is OPTION_REG_PS
end if
This seems a better normalisation': a similar naming for all timers.
The PIC_14H have a T0CON like the 18Fs, another reason to go in that
direction.
Adding these aliases to the device files seems a good idea. It would
result in 'cleaner' libraries: all timers controlled by 'TxCON_...',
even Timer0.
You may open a 'request for improvement' issue.
As you can see from my commit, I have updated servo lib to use timer0,
timer1 or timer3. Next, I will try to allow up to 24 servo's using all
3 timers, I already did some basic testing on this and it works!
Timer2 has a weird prescaller, I may not bother with it.
About servo.jal: I do not see a check for presence of timers. For
safety you could add a check "if defined(<timer>)" in servo.jal, not
all PICs have all timers and some have more than 4 timers.
You may also be more consequent in the use of upper and lower case (not
that the compiler will complain, but it looks neater).
Regards, Rob.
--
Rob Hamerling, Vianen, NL (http://www.robh.nl/)
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