Comment #7 on issue 171 by robhamerling: ADC group change for several
18Fxxk22 PICs
http://code.google.com/p/jallib/issues/detail?id=171
I have deleted comment #3 because it is inappropriate.
After re-reading several datasets I came to the following conclusions:
1. When an ANCONx register contains bits called ANSELi, these bits have to
be set to 0 to make the corresponding pin digital-I/O.
2. When the bits in ANCONx are called PCFGi the bits have to be set to '1'
to make the corresponding pin digital-I/O.
Currently the device files don't make this distinction: ANCON bits are
always set to 0 when enable_digital_io() is executed. Will try to fix this!
--
You received this message because you are subscribed to the Google Groups
"jallib" group.
To post to this group, send email to [email protected].
To unsubscribe from this group, send email to
[email protected].
For more options, visit this group at
http://groups.google.com/group/jallib?hl=en.
