My name is Udara De Silva and I am a Ph.D student from University of Akron.
I got familiar with Jenkins after I started using it in my project
https://chiphackers.com/. I am really looking forward to work on a Jenkins
project for this year GSOC, so that I can contribute to improve Jenkins.
Particularly I am interested in extending Jenkins capabilities for
Electronic Design Automation and Verification.
My familiar programming languages are JAVA, C++, Python and Matlab.
Relating to this project, I am familiar with Verilog and VHDL. Also I have
good experience in EDA tools like Design Compiler, Prime Time, SpyGlass,
VCS and Model Sim. I have also worked as a R&D Engineer at Synopsys before
starting my Ph.D. I have participated in GSOC 2015 while I was doing my
undergraduates. My project was to develop and hardware verify a SDRAM
Controller using MyHDL open source EDA module for Python. All my results
from the project can be found on my blog :
Below are few of my online profiles:
Linked In : https://www.linkedin.com/in/udara28/
GitHub : https://github.com/udara28
About the interested project: Continuous Integration in Electronic
Designing (Specially in IP development) is a true challenge. Jenkins
strength in Software CI (Continuous integration) can be used to solve this
challenge. An EDA plugin for Jenkins will have following features:
* Result reporting for unit tests, coverage ( coverage? need to study
the support for this feature from open source simulators.)
* Publicly accessible health status of the design
Udara De Silva
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