--- In [email protected], Greg Dyess <gregory.dy...@...> wrote:
>
> Try changing the label to A_BUS[0..15] instead of A_BUS[0,15]Â (Note the
> ".." instead of ",").
>
> In addition, I will load up your schematic and try to see what I can see.
>
> Greg
yes, I was burned here as well. An enhancement request for
EEschema would be to allow A_BUS[0..15] or A_BUS[0:15] like verilog
syntax...but A_BUS[0,15] in verilog would mean only 2 members
{A_BUS[0], A_BUS[15}. The missing feature is bundles, which would
allow grouping multiple buses and control lines into a single
bus (bundle) on the schematic or
assign MEM_BUS[50:0] = {ADR[31:0], DATA[15:0], \RD, \WRT, CLK};
MEM_BUS would be the sheet port name and the right hand members
part of the bus rippers. In verilog, this bidirectionaly wires:
MEM_BUS[50] to ADR[31]
MEM_BUS[49] to ADR[30]
....
MEM_BUS[1] to \WRT
MEM_BUS[0] to CLK
However implying this left to right assignment on a schematic
might be problematic. One work around is to use Global Lables
even though (for better documentation) it's nice to see the
members on a bus label!
The current approach promotes A_BUS[0..15] to
sub_sheet/A_BUS[0], sub_sheet/A_BUS[1]... sub_sheet/A_BUS[15]
as netnames for the parent and sub_sheet.
Bottom line is always check the netlist!
-Frank
>
>
>
>
> ________________________________
> From: Bob Shaffer <bob.shaf...@...>
> To: [email protected]
> Sent: Wednesday, June 24, 2009 9:13:47 AM
> Subject: RE: [kicad-users] Bad Bus Label error message when making netlist [1
> Attachment]
>
> [Attachment(s) from Bob Shaffer included below]
>
>
> Greg,
> I appreciate you taking the time to help me!
> Â
> The attached files represent a simple test design that illustrate my problem.
> When I try to connect the two sheets together by drawing a Bus between
> A_BUS[0,15] on Sheet A to A_BUS[0,15] on Sheet B I get a popup error message
> âBad Bus Labelâ. If I ignore the message and attempt to generate a
> netlist, I get the same error message.
> Â
> Bob
> Â
> Â
> From:[email protected] [mailto:[email protected]] On
> Behalf Of Greg Dyess
> Sent: Wednesday, June 24, 2009 9:23 AM
> To: [email protected]
> Subject: Re: [kicad-users] Bad Bus Label error message when making netlist
> Â
>
>
>
>
> My initial guesses would be:
> 1. You used a local label instead of a global label or net name.
> 2. Somehow numbers were not the last characters in the individual nets or the
> bus was not the prefix of the net names.
> 3. Buses in KiCAD are not like computer busses. Only nets with the same
> prefix followed by numbers are allowed in the bus. A0, A1, A2 in bus
> A[0..2] is a valid bus but WR, RD, CLK in bus Control is not valid.
> Â
> (I did all of the above starting out)
> It's difficult to analyze without seeing what you have done. If you email
> me directly with the archived project files I can load it up and see.
> Â
> Greg
>
> ________________________________
>
> From:mmabshaffer <bob.shaf...@...>
> To: [email protected]
> Sent: Tuesday, June 23, 2009 5:02:04 PM
> Subject: [kicad-users] Bad Bus Label error message when making netlist
>
> I just tried using KiCad for capturing a schematic and all went well until I
> tried to generate the netlist. I get a "Bad Bus Label" error popup message
> for each bus. The design is a hierarchical design with busses going between
> sheets. Can anyone give me a hint as to what I am doing wrong?
>
>
>
> ------------------------------------
>
> Please read the Kicad FAQ in the group files section before posting your
> question.
> Please post your bug reports here. They will be picked up by the creator of
> Kicad.
> Please visit http://www.kicadlib.org for details of how to contribute your
> symbols/modules to the kicad library.
> For building Kicad from source and other development questions visit the
> kicad-devel group at http://groups.yahoo.com/group/kicad-develYahoo! Groups
> Links
>
>
>
> Attachment(s) from Bob Shaffer
> 1 of 1 File(s)
> TestBoard.zip
>
