That's pretty much what I was thinking by a user pin system, but rather than a different pin as such it would be a override of an existing pin type. I was thinking (not very hard I'll admit) that a user pin could be specified to connect to one other pin and any user pin of the same type. So you could define a UP1 (user pin type one) specify that to connect to a device power out, then place UP1's on the parallel power pins of the device. User pin erc would override normal pin erc.
Now I'll agree that in the case of parallel power pins perhaps something that directly copes with such situations would be a good idea, but the system does need a method to cater for all the odd requirements that will crop up, without overloading the system too much. Your idea of a list to see what sort of problems people have run into is a good one. That would help judge the scope of the problem. The FPGA / Micro problem you mention may have a simpler solution. Almost what you say, but rather than defining a set of pins for an output, just having the ability to set the pin type via the schematic would do the job. Should a designer find themselves using the same pin set a number of times then changing the base setting in the lib would do most of the work. Obviously this would have to be a user setup operation as everyone would have their own idea or a default :-) Andy > > I think the DRC needs a rethink. Exceptions seems like using a hammer > to crack an egg. In the situation provided by having multiple voltage > output pins which is quite common, it's like you are trying to kick > the DRC to ignore this error, even though it is a valid error > according to the DRC rules. > > I think it would be better to be able to generate the rules necessary > to allow the DRC to correctly distinguish between errors, warnings and > passes. > > In the example given where there are multiple output power pins > connected together, it would seem that an output pin type could do > with other attributes to give the DRC enough information. For example > being able to flag an output pin as parallel capable, either globally > or within it's own symbol would get us a step closer and give us finer > control over the DRC. > > A valid situation for example is being able to parallel two DC-DC > converters *if* they are capable of being paralleled, the further > complication is correctly flagging and error where two DC-DC > converters which are capable of being paralleled are paralleled but > their output voltages differ! e.g. a 12V DC-DC paralleled with a 5V > DC-DC. > > In the case of FPGA's and Micro's, we could possibly do with being > able to define a set of pin types for a single pin. When the schematic > symbol is placed, we should perhaps be able to click on a pin and > change the pin type from an enum of pin types allowed for that pin. > > We could probably do with a list of situations/rules that cannot > currently be defined with the DRC, and then we can start tackling a > way of being able to define the appropriate rules. > > Does this sound reasonable, or a nightmare? > > Best Regards, > > Brian.
