On Mon, Mar 17, 2008 at 10:40:35AM -0700, Bob La Quey wrote:
The Intellasys SeaForth 24 chip was designed with the tools that you are disparaging. How would you have designed such a chip?
Probably more like the rest of the world does chip design. Honestly, I don't think normal chip design is very good either. And, I think that Moore's tools are a great step in the right direction. My problem with Forth in general is an ability to get far enough away from the hardware. Bit manipulation is fine when you are doing bit manipulation. Doing symbolic manipulation (chip design is entirely symbolic, nothing about the problem runs on the hardware that the design software runs on) does not involve. There is an unwillingness in forth to abstract away which keeps every thing down at this strange high and low level mixture. You can might high-level words, but they still hand pointers to things around.
The massive tools you talk about embedd a _lot_ of knowledge so that the average chip designer needs to know far less. This is both good and bad. Many argue thgat it is unrealistic becuase as in all things most chip designers are by definition just average and need all the help they can get.
Average chip designers aren't usually the ones producing massive complicated designs. Realistic massive designs are generally going to require custom software. The problem is that the set of engineers capable of writing custom software to design chips as well as have a deep understanding of hardware. Most hardware engineers don't get past simple abstractions and most software engineers seem to be afraid of the hardware. The existing chip design software is absolutely dreadful. I've run the Xilinx software that they provide for their low-end FPGAs. If any compiler company made a compiler that had such a crufty interfacae and so barely-worked, they would go out of business. The problem is that all of the HW tools are the same way. David -- [email protected] http://www.kernel-panic.org/cgi-bin/mailman/listinfo/kplug-lpsg
