[email protected] wrote:
What about smp?
fc will broadcast to the coherence domain the cache invalidation. So it is
SMP-ready for usual machines.
Interesting.
I'm surprised the guest doesn't do this by itself?
It doesn't had to do it. The PCI transaction will automatically invalidate
caches - but qemu doesn't emulate this (and doesn't need to do on x86).
So any DMA on ia64 will flush the instruction caches?!
--
error compiling committee.c: too many arguments to function
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