Avi Kivity wrote: > [email protected] wrote: >> >>> What about smp? >>> >> >> fc will broadcast to the coherence domain the cache invalidation. >> So it is SMP-ready for usual machines. >> >> > > Interesting. > >>> I'm surprised the guest doesn't do this by itself? >>> >> >> It doesn't had to do it. The PCI transaction will automatically >> invalidate caches - but qemu doesn't emulate this (and doesn't need >> to do on x86). >> > > So any DMA on ia64 will flush the instruction caches?
Yes, physical DMA should do this, but for virtual DMA operation emulated by Qemu should use explict intrusctions(fc, sync.i) to get it happen, because the data transferred by virtual DMA maybe used as instrustion streams by guest. Xiantao-- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
