Avi Kivity wrote: > Avi Kivity wrote: >>>> >>> >>> It doesn't had to do it. The PCI transaction will automatically >>> invalidate caches - but qemu doesn't emulate this (and doesn't need >>> to do on x86). >>> >> >> So any DMA on ia64 will flush the instruction caches?! >> > > Or maybe, the host kernel will do it after the transaction completes?
Host kernel doesn't do anything about cache flush after DMA, since it thinks platform guarantees that. > In our case the lack of zero-copy means the host is invalidating the > wrong addresses (memcpy source) and leaving the real destination > intact. We just need to sync the target address(destination address), because only its physical address belongs to guest, and likely to be the DMA target address of guest. Xiantao -- To unsubscribe from this list: send the line "unsubscribe kvm" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
