On 8/22/2018 1:47 PM, Mikulas Patocka wrote:
If ARM guarantees that the accesses to a given device are not reordered - then the barriers in readl and writel are superfluous.
It is not. ARM only guarantees ordering of read/write transactions targeting a device not memory. example: write memory raw write to device or raw read from device read memory these can bypass each other on ARM unless a barrier is placed in the right place either via readl()/writel() or explicitly. raw write to device raw write to device or raw write to device raw read from device or raw read from device raw read from device are guaranteed to be ordered on ARM without needing any explicit barrier.
