Re: Alpha Avanti broken by 9ce8654323d69273b4977f76f11c9e2d345ab130

[Mikulas Patocka]

On Wed, 22 Aug 2018, Sinan Kaya wrote:

> On 8/22/2018 1:47 PM, Mikulas Patocka wrote:
> > If ARM guarantees that the accesses to a given device are not reordered -
> > then the barriers in readl and writel are superfluous.
> 
> It is not. ARM only guarantees ordering of read/write transactions targeting
> a device not memory.
> 
> example:
> 
> write memory
> raw write to device
> 
> or
> 
> raw read from device
> read memory
> 
> these can bypass each other on ARM unless a barrier is placed in the right
> place either via readl()/writel() or explicitly.

Yes - but - why does Linux insert the barriers into readl() and writel() 
instead of inserting them between accesses to registers and memory?

A lot of drivers have long sequences of accesses to memory-mapped 
registers with no interleaving accesses to coherent memory and these 
implicit barriers slow them down with no gain at all.

Mikulas