Re: [PATCH] alpha: add barrier before writing to the hae register

[Mikulas Patocka]

On Wed, 22 Aug 2018, Richard Henderson wrote:

> On 08/22/2018 01:42 PM, Mikulas Patocka wrote:
> >     unsigned long flags = swpipl(IPL_MAX);
> >  
> > -   barrier();
> > +   mb();
> 
> Maybe, but I doubt it makes a difference in practice.
> 
> The swpipl is a transition through PALcode, and the
> instruction queue will have been flushed into and out
> of PALmode.

Architecturally, PAL calls aren't memory barriers. It's hard to tell 
whether they are in practice.

The possible problem here is reordering inside the chipset, not inside the 
CPU (ev45 is in-order). And the chipset doesn't care whether the CPU is 
executing inside PAL or not.

> But of course the barrier shouldn't be required either.
> 
> 
> r~

Mikulas