[PATCH 12/25] dts: unisoc: rda8810pl: Add OPP for CPU and define L2 cache

[Dang Huynh via B4 Relay]

From: Dang Huynh <dang.hu...@mainlining.org>

Add available frequency table came from downstream kernel, this
ensures that the CPU clock can be dynamically tuned.

Signed-off-by: Dang Huynh <dang.hu...@mainlining.org>
---
 arch/arm/boot/dts/unisoc/rda8810pl.dtsi | 52 +++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi 
b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi
index 
1f7a6908d68367441e5dc865216cc7a5c39feb35..299b29e4df6e0a04c5769a568eba73ed1684a9e5
 100644
--- a/arch/arm/boot/dts/unisoc/rda8810pl.dtsi
+++ b/arch/arm/boot/dts/unisoc/rda8810pl.dtsi
@@ -16,6 +16,54 @@ / {
        #address-cells = <1>;
        #size-cells = <1>;
 
+       /*
+        * There are two frequency table for CPU.
+        *
+        * "High" table is used when operating in normal mode
+        * "Low" table is used when operating in power saving mode
+        */
+       cpu_high_opp_table: opp-table-0 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-329333333 {
+                       opp-hz = /bits/ 64 <329333333>;
+               };
+
+               opp-395200000 {
+                       opp-hz = /bits/ 64 <395200000>;
+               };
+
+               opp-494000000 {
+                       opp-hz = /bits/ 64 <494000000>;
+               };
+
+               opp-988000000 {
+                       opp-hz = /bits/ 64 <988000000>;
+               };
+       };
+
+       cpu_low_opp_table: opp-table-1 {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp-266666666 {
+                       opp-hz = /bits/ 64 <266666666>;
+               };
+
+               opp-320000000 {
+                       opp-hz = /bits/ 64 <320000000>;
+               };
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+               };
+
+               opp-800000000 {
+                       opp-hz = /bits/ 64 <800000000>;
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
@@ -24,6 +72,10 @@ cpu@0 {
                        device_type = "cpu";
                        compatible = "arm,cortex-a5";
                        reg = <0x0>;
+                       next-level-cache = <&l2>;
+
+                       clocks = <&ap_syscon CLK_CPU>;
+                       operating-points-v2 = <&cpu_high_opp_table>;
                };
        };
 

-- 
2.51.0