Title: [6876] trunk/arch/blackfin: Fix bug[#5287] Don't flush cache in L1 SRAM.
Revision
6876
Author
sonicz
Date
2009-06-30 04:48:03 -0500 (Tue, 30 Jun 2009)

Log Message

Fix bug[#5287] Don't flush cache in L1 SRAM.

L1 instruction SRAM is not cachable. Executing Flush, flushinv or iflush
in this address region on bf533 v0.3 triggers double fault exception.
Although no double fault on other bfin chips, it is safe not to do it.

Modified Paths

Diff

Modified: trunk/arch/blackfin/Kconfig (6875 => 6876)


--- trunk/arch/blackfin/Kconfig	2009-06-30 09:38:43 UTC (rev 6875)
+++ trunk/arch/blackfin/Kconfig	2009-06-30 09:48:03 UTC (rev 6876)
@@ -987,7 +987,7 @@
 config BFIN_L2_DCACHEABLE
 	bool "Enable DCACHE for L2 SRAM"
 	depends on BFIN_DCACHE
-	depends on BF54x || BF561
+	depends on (BF54x || BF561) && !SMP
 	default n
 choice
 	prompt "L2 SRAM DCACHE policy"
@@ -995,11 +995,9 @@
 	default BFIN_L2_WRITEBACK
 config BFIN_L2_WRITEBACK
 	bool "Write back"
-	depends on !SMP
 
 config BFIN_L2_WRITETHROUGH
 	bool "Write through"
-	depends on !SMP
 endchoice
 
 

Modified: trunk/arch/blackfin/include/asm/cacheflush.h (6875 => 6876)


--- trunk/arch/blackfin/include/asm/cacheflush.h	2009-06-30 09:38:43 UTC (rev 6875)
+++ trunk/arch/blackfin/include/asm/cacheflush.h	2009-06-30 09:48:03 UTC (rev 6876)
@@ -56,9 +56,14 @@
 
 static inline void flush_icache_range(unsigned start, unsigned end)
 {
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
-	blackfin_dcache_flush_range(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
+	if (start >= 0x1000 && end <= physical_mem_end)
+		blackfin_dcache_flush_range(start, end);
 #endif
+#if defined(CONFIG_BFIN_L2_WRITEBACK)
+	if (start >= L2_START && end <= L2_START + L2_LENGTH)
+		blackfin_dcache_flush_range(start, end);
+#endif
 
 	/* Make sure all write buffers in the data side of the core
 	 * are flushed before trying to invalidate the icache.  This
@@ -69,10 +74,18 @@
 	 * the pipeline.
 	 */
 	SSYNC();
-#if defined(CONFIG_BFIN_ICACHE)
-	blackfin_icache_flush_range(start, end);
-	flush_icache_range_others(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
+	if (start >= 0x1000 && end <= physical_mem_end) {
+		blackfin_icache_flush_range(start, end);
+		flush_icache_range_others(start, end);
+	}
 #endif
+#if defined(CONFIG_BFIN_L2_ICACHEABLE)
+	if (start >= L2_START && end <= L2_START + L2_LENGTH) {
+		blackfin_icache_flush_range(start, end);
+		flush_icache_range_others(start, end);
+	}
+#endif
 }
 
 #define copy_to_user_page(vma, page, vaddr, dst, src, len)		\
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