Modified: trunk/arch/blackfin/kernel/process.c (7488 => 7489)
--- trunk/arch/blackfin/kernel/process.c 2009-09-28 09:20:57 UTC (rev 7488)
+++ trunk/arch/blackfin/kernel/process.c 2009-09-28 09:21:51 UTC (rev 7489)
@@ -366,6 +366,8 @@
#ifdef COREB_L1_CODE_START
if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
+ if (in_mem_const(addr, size, COREB_L1_CODECACHE_START, COREB_L1_CODECACHE_LENGTH))
+ return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
@@ -486,6 +488,8 @@
#ifdef COREB_L1_CODE_START
if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
return 1;
+ if (in_mem_const(addr, size, COREB_L1_CODECACHE_START, COREB_L1_CODECACHE_LENGTH))
+ return 1;
if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
return 1;
if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
Modified: trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h (7488 => 7489)
--- trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h 2009-09-28 09:20:57 UTC (rev 7488)
+++ trunk/arch/blackfin/mach-bf561/include/mach/mem_map.h 2009-09-28 09:21:51 UTC (rev 7489)
@@ -41,6 +41,7 @@
#define COREA_L1_DATA_A_START 0xFF800000
#define COREA_L1_DATA_B_START 0xFF900000
#define COREB_L1_CODE_START 0xFF600000
+#define COREB_L1_CODECACHE_START 0xFF610000
#define COREB_L1_DATA_A_START 0xFF400000
#define COREB_L1_DATA_B_START 0xFF500000
@@ -92,9 +93,31 @@
# define COREB_L1_DATA_A_LENGTH L1_DATA_A_LENGTH
# define COREB_L1_DATA_B_LENGTH L1_DATA_B_LENGTH
#else
-# define COREB_L1_CODE_LENGTH 0x14000
-# define COREB_L1_DATA_A_LENGTH 0x8000
-# define COREB_L1_DATA_B_LENGTH 0x8000
+
+# define COREB_L1_CODE_LENGTH 0x4000
+
+# ifdef CONFIG_BFIN_COREB_ICACHE
+# define COREB_L1_CODECACHE_LENGTH 0x0
+# else
+# define COREB_L1_CODECACHE_LENGTH 0x4000
+# endif
+
+# ifdef CONFIG_BFIN_COREB_DCACHE
+# ifdef CONFIG_BFIN_COREB_DCACHE_BANKA
+# define COREB_DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+# define COREB_L1_DATA_A_LENGTH 0x4000
+# define COREB_L1_DATA_B_LENGTH 0x8000
+# else
+# define COREB_DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+# define COREB_L1_DATA_A_LENGTH 0x4000
+# define COREB_L1_DATA_B_LENGTH 0x4000
+# endif
+# else
+# define COREB_DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+# define COREB_L1_DATA_A_LENGTH 0x8000
+# define COREB_L1_DATA_B_LENGTH 0x8000
+# endif
+
#endif
/* Level 2 Memory */
