On Tue, 2009-09-29 at 09:24 -0400, Robin Getz wrote:
> On Mon 28 Sep 2009 21:59, graff.yang pondered:
> > On Mon, 2009-09-28 at 15:17 -0400, Mike Frysinger wrote:
> > > On Mon, Sep 28, 2009 at 05:21,  <[email protected]> wrote:
> > > > Revision 7489 Author gyang Date 2009-09-28 05:21:51 -0400 (Mon, 28
> > Sep 2009)
> > > >
> > > > Log Message
> > > >
> > > > seperate defines about l1 code/cache and code only sram
> > > 
> > > why ?  the entire point was that treating it as one contiguous blob
> > 
> > Task [#4788], dsp-bridge may write code to l1, it's dangerous, if there
> > is a gap between COREB_L1_CODE_START to COREB_L1_CODE_START +
> > L1_CODE_LENGTH.
> 
> Before we have a spec that everyone agrees to - we should not be making 
> changes to kernel code that is going to slow down all accesses on every part.
OK, I'd revert this change soon.

> 
> See the comments on the task tracked for more info.
> 


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