On Wed, Dec 02, 2015 at 09:37:05AM +0100, Arnd Bergmann wrote: > The 4*PAGE_SIZE on ARM is an architecture specific oddity, I believe > to work around aliasing caches on ARMv6. As no other architecture does > this, we're probably better off not duplicating it for aarch64-ilp32 > and just use sys_shmat as your v6 patch does. > Arnd
If you feel ARMv6 fix for caches will come soon, just ignore it. Otherwise, please pull it because compat_sys_shmat is broken now for 64K pages. Signed-off-by: Yury Norov <yno...@caviumnetworks.com> --- arch/arm64/include/asm/shmparam.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/shmparam.h b/arch/arm64/include/asm/shmparam.h index 4df608a..e368a55 100644 --- a/arch/arm64/include/asm/shmparam.h +++ b/arch/arm64/include/asm/shmparam.h @@ -21,7 +21,7 @@ * alignment value. Since we don't have aliasing D-caches, the rest of * the time we can safely use PAGE_SIZE. */ -#define COMPAT_SHMLBA 0x4000 +#define COMPAT_SHMLBA (4 * PAGE_SIZE) #include <asm-generic/shmparam.h> -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
