Commit-ID:  eeab3eee2fa4a8e8eb52e2abf034f14f1d010e0d
Gitweb:     https://git.kernel.org/tip/eeab3eee2fa4a8e8eb52e2abf034f14f1d010e0d
Author:     Tom Lendacky <thomas.lenda...@amd.com>
AuthorDate: Fri, 5 Jan 2018 10:08:05 -0600
Committer:  Thomas Gleixner <t...@linutronix.de>
CommitDate: Sat, 6 Jan 2018 21:57:41 +0100

x86/msr: Remove now unused definition of MFENCE_RDTSC feature

With the switch to using LFENCE_RDTSC on AMD platforms there is no longer
a need for the MFENCE_RDTSC feature.  Remove its usage and definition.

Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com>
Signed-off-by: Thomas Gleixner <t...@linutronix.de>
Reviewed-by: Borislav Petkov <b...@alien8.de>
Cc: Peter Zijlstra <pet...@infradead.org>
Cc: Linus Torvalds <torva...@linux-foundation.org>
Cc: Dave Hansen <dave.han...@intel.com>
Cc: Tim Chen <tim.c.c...@linux.intel.com>
Cc: Greg Kroah-Hartman <gre...@linux-foundation.org>
Cc: David Woodhouse <d...@amazon.co.uk>
Cc: Paul Turner <p...@google.com>
Cc: sta...@vger.kernel.org
Link: 
https://lkml.kernel.org/r/20180105160805.23786.5177.st...@tlendack-t1.amdoffice.net

---
 arch/x86/include/asm/cpufeatures.h | 2 +-
 arch/x86/include/asm/msr.h         | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/x86/include/asm/cpufeatures.h 
b/arch/x86/include/asm/cpufeatures.h
index 1641c2f..511d909 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -96,7 +96,7 @@
 #define X86_FEATURE_SYSCALL32          ( 3*32+14) /* "" syscall in IA32 
userspace */
 #define X86_FEATURE_SYSENTER32         ( 3*32+15) /* "" sysenter in IA32 
userspace */
 #define X86_FEATURE_REP_GOOD           ( 3*32+16) /* REP microcode works well 
*/
-#define X86_FEATURE_MFENCE_RDTSC       ( 3*32+17) /* "" MFENCE synchronizes 
RDTSC */
+/* free, was: #define X86_FEATURE_MFENCE_RDTSC ( 3*32+17)  "" MFENCE 
synchronizes RDTSC */
 #define X86_FEATURE_LFENCE_RDTSC       ( 3*32+18) /* "" LFENCE synchronizes 
RDTSC */
 #define X86_FEATURE_ACC_POWER          ( 3*32+19) /* AMD Accumulated Power 
Mechanism */
 #define X86_FEATURE_NOPL               ( 3*32+20) /* The NOPL (0F 1F) 
instructions */
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 07962f5..8d8d7ae 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -214,8 +214,7 @@ static __always_inline unsigned long long 
rdtsc_ordered(void)
         * that some other imaginary CPU is updating continuously with a
         * time stamp.
         */
-       alternative_2("", "mfence", X86_FEATURE_MFENCE_RDTSC,
-                         "lfence", X86_FEATURE_LFENCE_RDTSC);
+       alternative("", "lfence", X86_FEATURE_LFENCE_RDTSC);
        return rdtsc();
 }
 

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