On 12/02/18 18:27, Marc Zyngier wrote:
On 12/02/18 18:17, Sudeep Holla wrote:
On 07/02/18 14:32, Marc Zyngier wrote:
From: Robin Murphy <robin.mur...@arm.com>
Juno's GICv2m implementation consists of four frames providing 32
interrupts each. Since it is possible to plug in enough PCIe endpoints
to consume more than 32 MSIs, and the driver already has a bodge to
handle multiple frames, let's expose the other three as well.
Change on it own looks good. So if you want to merge via your tree:
Acked-by: Sudeep Holla <sudeep.ho...@arm.com>
Let me know if you decide not to take it via your tree and you want me
to send it to arm-soc.
If this would usually go via arm-soc, feel free to take it via this
route. I'll drop the patch from my tree.
On the side note I just noticed the Juno TRM has 64k for each of
these MSI frames(page 3-24 section 3.3.5 Application memory map summary)
I am not sure if TRM is wrong. This patch is just copying the 4k size
from frame 0 which got added with initial Juno DTS.
I can't see why the TRM would be wrong. This is actually consistent with
the expected practice of aligning all devices on a 64kB boundary and
size so that you don't get any nasty surprise when passing the device to
a VM (*cough* GIC400 *cough*).
Robin, any chance you could check this?
Well, the engineering spec for the v2m widget does claim that only the
bottom 12 bits of AxADDR are used, but on the other hand it also implies
that the "real" endpoint here is a single monolithic block of 4 such
widgets, so a third truth is that there is only a single 256KB region...
As usual, I've completely forgotten about virtualisation when it comes
to hardware :) On reflection I do of course appreciate that whilst 60KB
of RAZ/WI space isn't significant in terms of "a device", it is rather
more so in terms of "not a device" - if the only reasonable way to
communicate that is to describe the v2m devices each owning 64KB, then
I'm quite happy for you to fix up the patch that way if you want.