On Mon, Sep 10, 2018 at 10:41:22PM +0530, Anup Patel wrote: > RISC-V priv spec 1.10 defines the 9 bits in MIE and MIP registers and > other bits are reserved. > > The unused bits in MIP are WIRI (reserved write ignored and read ignored) > and unused bits in MIE are WPRI (reserved write preserve values and > read ignored). > > The RISC-V priv spec 1.10 does not tell that unused reserved bits in > MIE/MIP cannot be used for: > 1. CPU implementation specific local interrupts > 2. Per-CPU device interrupts. > > The RISC-V priv spec 1.10 tries to only describe MIE/MIP bits which > are mandatory on any RISC-V 1.10 compliant CPU but it possible to > used other reserved bits for implementation specific local interrupts.
Reserved means reserved for future versions of the spec, not for vendor specific bad ideas.
