The sifive_l2_cache.c is in no way related to RISC-V architecture
memory management. It is a little stub driver working around the fact
that the EDAC maintainers prefer their drivers to be structured in a
certain way that doesn't fit the SiFive SOCs.
Move the file to drivers/misc and only build it when the EDAC_SIFIVE
config option is selected.
Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller driver
for SiFive SoCs")
Signed-off-by: Christoph Hellwig <[email protected]>
---
arch/riscv/mm/Makefile | 1 -
drivers/misc/Makefile | 1 +
{arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
3 files changed, 1 insertion(+), 1 deletion(-)
rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 74055e1d6f21..d2101d0741d4 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -11,6 +11,5 @@ obj-y += extable.o
obj-y += ioremap.o
obj-y += cacheflush.o
obj-y += context.o
-obj-y += sifive_l2_cache.o
obj-$(CONFIG_HUGETLB_PAGE) += hugetlbpage.o
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index abd8ae249746..886d48301e8e 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -59,3 +59,4 @@ obj-y += cardreader/
obj-$(CONFIG_PVPANIC) += pvpanic.o
obj-$(CONFIG_HABANA_AI) += habanalabs/
obj-$(CONFIG_XILINX_SDFEC) += xilinx_sdfec.o
+obj-$(CONFIG_EDAC_SIFIVE) += sifive_l2_cache.o
diff --git a/arch/riscv/mm/sifive_l2_cache.c b/drivers/misc/sifive_l2_cache.c
similarity index 100%
rename from arch/riscv/mm/sifive_l2_cache.c
rename to drivers/misc/sifive_l2_cache.c
--
2.20.1
