On Wed, Aug 07, 2019 at 05:22:15PM +0200, Greg KH wrote:
> > Fixes: a967a289f169 ("RISC-V: sifive_l2_cache: Add L2 cache controller
> > driver for SiFive SoCs")
> > Signed-off-by: Christoph Hellwig <[email protected]>
> > ---
> > arch/riscv/mm/Makefile | 1 -
> > drivers/misc/Makefile | 1 +
> > {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c | 0
> > 3 files changed, 1 insertion(+), 1 deletion(-)
> > rename {arch/riscv/mm => drivers/misc}/sifive_l2_cache.c (100%)
>
> Why isn't this in drivers/edac/ ?
> why is this a misc driver? Seems like it should sit next to the edac
> stuff.
No idea. EDAC maintainers, would you object to taking what is
currently in arch/riscv/mm//sifive_l2_cache.c to drivers/edac/ ?
